2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Vector Control of Permanent Magnet Synchronous Machine with Reduced Switch Five-Level Voltage Source Inverter","authors":"R. Mahto, A. Mishra","doi":"10.1109/EPTC47984.2019.9026670","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026670","url":null,"abstract":"This paper presents a six switch five-level (0, ±Vdc/2, ±Vdc) VSI (voltage source inverter) fed PMSM (permanent magnet synchronous motor) drive. The circuit topology and number of switching devices are same as that of basic three phase two-level voltage source inverter. The implementation of reduced switch 5-level inverter improves the pulsating torque and dynamic speed response under various operating conditions. The concept of vector control is applied to obtain good dynamic performance and the machine can also be control like separately excited DC motor. Three PI controllers is employed as speed, torque, and flux controller and PWM technique is used to trigger switches of six switch 5-level inverter. The circuit configuration and PMSM model are developed in MATLAB/SIMULINK environment and the performance is investigated with change in speed and load torque. Based upon simulation result the performance of proposed technique is recommended for significant reduction in THD (total harmonics distortion) of stator current and ripple in electromagnetic torque without increased in additional cost of overall system.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"343 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132893177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"InkJet Printing As Alternative Approach To Conventional Spin-on Material Coatings","authors":"P. Miskiewicz, M. Koch, D. Walker, F. Meyer, S. Wieder, James Haley, V. Dutta","doi":"10.1109/EPTC47984.2019.9026661","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026661","url":null,"abstract":"Polymer dielectrics have been in use for various layers in IC packages starting from substrates up to Epoxy Molding Compounds. There is a variety of various polymer chemistry approaches applied, mainly polyimides, polybenzoxazoles, epoxy resins and benzocyclobutene. Processing from solution in combination with photolithography has been the main technique to make small features e.g. for Re-Distribution Layer (RDL) or Stress Buffer (SB) applications. That method has been perfected over the years and delivers the required patterns and yield on the production. It is considered as standard process by default for enabling the assembly of flip-chip packages. However, spin-coating followed by photolithography is known to be rather wasteful, with only 10-20% of material staying on the substrate after patterning - all because it is subtractive method. In this paper we present InkJet printing as an alternative additive method approach for selected applications, where features' resolution is pushing beyond 20-50um line/spacing.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"504 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133548919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra High Density Package Design and Electrical Analysis in High Performance Computing Application","authors":"Tsun-Lung Hsieh, H. Kuo, Ming-Fong Jhong, Chih-Yi Huang, Chen-Chao Wang","doi":"10.1109/EPTC47984.2019.9026605","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026605","url":null,"abstract":"With regard to the development of the Internet of Things, artificial intelligence, autonomous driving and the robotic development applications, the high bandwidth and low latency performance are needed. In this trend, the high performance semiconductor integrated package have become an important product, such as FOCoS(Fan-out Chip on Substrate) and 2.5D Interposer which applied in high performance computing (HPC). The first application used in this kind ultra-high density package is high performance computing (HPC) like GPU, there is an ASIC die and multi-HBM dies on fan-out or silicon interposer structure. Between ASIC die and HBM die, there are lots of high speed signal lines, and lots of metal grid, vias for power/ground domain. A real product with an ASIC die and 2 HBM dies is designed in Chip Last FOCoS and 2.5D interpsoer structures, the FOCoS and 2.5D interposer design is utilized SiP-id (System in Package intelligent design) design platform to accelerate the ultra-high density I/O routings design cycle time. In electrical performacne, the signal integrity and power integrity are compared between FOCoS and 2.5D interposer. The signal eye-diagram of HBM2 and 28Gbps SerDes I/Os are showed in this paper, and the PDN power impedance is also analyzed. This paper is also studied how to optimize the copper coverage rate and DC resistance for core power/ground domain. Both FOCoS and 2.5D interposer ultra high denstiy package structures have a good opportunity in high performance computing application.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"17 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115724650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Epoxy Mold Compound Curing Behavior and Mold Process Cure Time Interaction on Molded Package Performance","authors":"April Joy H. Garete, Marlon F. Fadullo, Reinald John S. Roscain","doi":"10.1109/EPTC47984.2019.9026644","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026644","url":null,"abstract":"Epoxy mold compound curing behavior is a fundamental material property which affects the molding process and molded package performance. This paper aims to understand the effect of different cure time settings at isothermal conditions on mold compound material properties, molding process, and package quality and reliability through material characterization, thermal analysis, moldability, delamination response, package bending strength measurements and reliability testing. Overall results showed that longer mold cure time results to an increase in curing density due to better crosslinking of the epoxy-resin network and corresponds to improved mechanical properties and adhesion. Package delamination response and bending strength also improved with longer cure time. Moisture absorption and reliability were not affected by the different mold cure time settings after PMC was applied during assembly process. Understanding the interaction of mold compound curing behavior and optimum molding cure time parameter on molded package performance results to significant manufacturing productivity and equipment capacity improvement without sacrificing desired material properties, package integrity and reliability.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115746075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interfacial Microstructure Evolution for Cu/Cu3Sn/Cu Solder Joints during Ultrasonic-Assisted TLP Soldering Process","authors":"Xu Han, Xiaoyan Li, P. Yao, Dalong Chen","doi":"10.1109/EPTC47984.2019.9026609","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026609","url":null,"abstract":"In this study, the interfacial microstructure evolution and mechanism of ultrasonic action during ultrasonic-assisted TLP soldering process (260°C, 600W, 20KHz) were investigated. The bonding time forming full Cu<inf>3</inf>Sn solder joints of traditional TLP and ultrasonic-assisted TLP soldering was 600min and 50s respectively. Before forming full IMCs solder joints, the Cu<inf>6</inf>Sn<inf>5</inf> at Cu/Sn interface grew in a non-scallop-like shape during ultrasonic-assisted TLP soldering process, meanwhile, the non-interfacial Cu<inf>6</inf>Sn<inf>5</inf> distributed within the Sn layer, the Cu<inf>3</inf>Sn at Cu/Cu<inf>6</inf>Sn<inf>5</inf> interface grew in a non-wave-like shape or non-planar-like shape, the non-interfacial Cu<inf>3</inf>Sn in the Cu<inf>6</inf>Sn<inf>5</inf> contacted with the Cu<inf>3</inf>Sn layers at Cu/Cu<inf>6</inf>Sn<inf>5</inf> interface with the increasing of ultrasonic bonding time, which was different from the formation of scallop-like Cu<inf>6</inf>Sn<inf>5</inf> layers, wave-like and planar-like Cu<inf>3</inf>Sn layers by traditional TLP soldering. The mechanism of ultrasonic action was regarded as that the solder joints experience generation of micro-cracks in the Cu<inf>6</inf>Sn<inf>5</inf>, separation from Cu<inf>6</inf>Sn<inf>5</inf> layers at Cu/Sn interface, being smashed to smaller size of separate Cu<inf>6</inf>Sn<inf>5</inf> and moving into the liquid Sn of smaller Cu<inf>6</inf>Sn<inf>5</inf> in turn, while the formation of non-wave-like or non-planar-like Cu<inf>3</inf>Sn layers was considered to be the precipitation at Cu<inf>3</inf>Sn/Cu<inf>6</inf>Sn<inf>5</inf> interface of Cu atoms, the formation of non-interfacial CU3Sn was attributed to the traversing Cu<inf>3</inf>Sn layers at Cu/Cu<inf>6</inf>Sn<inf>5</inf> interface into Cu<inf>6</inf>Sn<inf>5</inf> of Cu atoms. In addition, the ultrasonic wave accelerated the diffusion of Cu atoms and Sn atoms to form IMCs.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117209898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Piezoelectric Energy Harvester Chip Fabrication and Vacuum Packaging","authors":"Zhipeng Ding, N. M. Sang, Han Beibei, P. Kee","doi":"10.1109/EPTC47984.2019.9026615","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026615","url":null,"abstract":"MEMS energy harvesters have attracted much interest in the area of wireless sensors as a potential standalone power source with small form factor. In this paper, we reported the fabrication, the vacuum packaging and the characterization of MEMS (Micro Electro-Mechanical Systems) piezoelectric energy harvester (EH). AlN (Aluminium Nitride) thin-film was adopted as the piezoelectric functional material to harvest vibrational mechanical energy utilising its electro-mechanical coupling capability. The device comprises suspended Al/AlN/Mo/Si cantilever as the energy harvesting structure and the proof mass made of bulk silicon which is formed by deep reactive ion etching (DRIE). The piezoelectric energy harvester device was fabricated on 8″ SOI (silicon on insulator) wafer ($30mu mathrm{m}$ Si device layer / $1mu mathrm{m}$ buried SiO2 / $725 mu mathrm{m}$ Si handle layer) by using 5 masks processes including 4 mask lithography processes from front side (bottom Mo, Piezoelectric AlN, top Al, and top Al/Si patterning) and 1 mask layer from backside ($400 mu mathrm{m}$ Si structural release). Ceramic LCC (leadless chip carrier) packages were used for the chip-scale vacuum packaging of the piezoelectric energy harvesters to minimize the energy loss from the air damping. The energy harvester was wire-bonded to metal pad inside ceramic packages. The getter layer was deposited by SAES on the inside of the lid and the getter was activated during the sealing process to achieve the intended vacuum inside the packages. The functionality of the energy harvester was tested at the probe station with a vacuum chamber before packaging and retested after chip-scale vacuum packaging to confirm the vacuum performance. To characterize the device, the generated open-circuit voltage between vacuum and no vacuum were measured and compared at 2g alternating accelerations. The generated voltage under open-circuit condition can reach around twice as that from the vacuum condition as at the ambient pressure. The Q factor of the energy harvester was calculated using the measured value in frequency domain. The Q factor of is about 750 in ambient pressure and 936 at vacuum. Higher Q at vacuum indicates a lower energy loss by air damping so higher open-circuit voltage can be generated at vacuum. The test results prove the MEMS integration platform and the chip-scale vacuum packaging work together successfully and the proposed approach can be used in other vibrational MEMS devices based on similar structures using AlN stack.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129748972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3D Interconnect through Conventional Pad by Via-last-from-top Approach","authors":"H. Li, Ling Xie, S. Chong","doi":"10.1109/EPTC47984.2019.9026632","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026632","url":null,"abstract":"To reduce 3D production time, TSV cavity and TSV on conventional Al pads were successfully designed, developed and demonstrated for 3D connection by via-last-from-top (VLFT) approach. Electrical connection through TSV cavity and TSV of 3D stacking was characterized and reported after assembly.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low-Power CMOS Temperature Sensor for On-Chip Thermal Gradient Detection","authors":"S. Harb, W. Eisenstadt","doi":"10.1109/EPTC47984.2019.9076729","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9076729","url":null,"abstract":"In this paper, a low-power CMOS temperature sensor based on a diode-connected NMOS FET is proposed. A sub-1V voltage reference is adopted to generate a temperature-invariant current source to bias the sensor device. The temperature sensing NMOS transistor is sized to maximize the temperature sensitivity. The proposed design is simulated based on 90 nm CMOS process technology, which shows temperature sensitivity of 0.25 mV/0C with a temperature range of from 00C to 1000C.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127158262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A New Die Attach Material for High Power Electronic Devices","authors":"Zhang Ruifen, Donald Nantes, Teo Lingling","doi":"10.1109/EPTC47984.2019.9026631","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026631","url":null,"abstract":"Solder paste is selected as one of the most widely used die attach materials in high power electronic devices. It plays the role to connect die on the substrate or connect copper clip on the die. It is important to get a uniform solder distribution and low void to ensure good electrical conductivity, excellent thermal conductivity as well as mechanical support for the high-power electronic devices, especially for the package with high current density and high operating temperature. Due to the wetting effect of the molten solder during reflow, the die will move and may result into non-uniform solder distribution between die and substrate. In addition, molten solder is not strong enough against the weight of heavy copper clip applied on it to achieve a desired bond line thickness (BLT). To improve the solder distribution uniformity and get desired bond line thickness, a novel die attach material will be discussed in this paper. This novel die attach material is a solder paste with addition of Cu sphere. The existence of the Cu sphere in solder paste will ease the unbalanced wetting force of liquidus solder during reflow process, the die tilt was reduced significantly compared to the solder paste without Cu sphere. At the same time, the addition of Cu sphere will increase the strength of the molten solder and reduce the spreading caused by the heavy copper clip, it is helpful to obtain a higher bond line thickness for copper clip application.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130166089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quality & Reliability Assessment of USB-PLL Clock Failure in Silicon Products","authors":"M. Pandey, Aanand Kr Sinha, P. K. Sharma, Rohit Sharma","doi":"10.1109/EPTC47984.2019.9026652","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026652","url":null,"abstract":"Quality and reliability are one of the crucial test features in post silicon validation which ensures the performance of flawless silicon production. This paper addresses the issue related to random clock valid failure of USB-PLL during the series of reliability testing on 28nm SoC product. However, in existence of such an unpredictable issue, silicon production cannot happen; though during the design verification and functional validation, the USB PLL clock valid was working as per design. To avoid production discontinuation, a permanent solution is need of the hour. So, this issue has been replicated on analog bench validation for further debugging and root-causing. During the debugging, PHY's clock validity issue was isolated and PLL clock was not obtained at digital logic of the USB. Thus, we propose the immediate solution for this product-level reliability problem by adding a reset sequence through a software setting. In addition to above, designers have been requested for thorough review of robustness of the oscillator concept to optimize this issue from designer perspective.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132317644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}