2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"A Process Study of Laser Patterning of Different Conductive Layers for Printed Electronics","authors":"Wenhe Feng, X. Shan, G. Lim","doi":"10.1109/EPTC47984.2019.9026689","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026689","url":null,"abstract":"Patterning of different conductive materials utilising nanosecond laser ablation was studied. The materials are namely printed silver (Ag) electrodes, laminated aluminium (Al) films, ITO thin films and PEDOT:PSS conductive polymer thin layer of different thicknesses. The authors investigated the feasibility of using 1064 nm wavelength, 20 nanosecond pulsed laser beam to strip off the conductive layers in order to electrically isolate the large area conductive materials or traces into appropriate segments or patterns. More importantly, the ablation process could be controlled to induce minimal interference to the underlying supporting materials while removing completely the conductive layer with very little residue. The ablated track widths the authors achieved in this project depends on the coating material and process parameters. Typically, the minimum line widths obtained using the laser patterning system were $60 mu mathrm{m}$ for printed silver, $33 mu mathrm{m}$ for Al, $28 mu mathrm{m}$ for ITO layer and $32 mu mathrm{m}$ for PEDOT:PSS, respectively.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125501044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Behavior of Resorcinol based Phthalonitrile as High Temperature Encapsulant","authors":"Yu Shan Tay, Jian Rong Eric Phua, C. Gan","doi":"10.1109/EPTC47984.2019.9026569","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026569","url":null,"abstract":"The increasing demand of harsh environment applications have propelled the engineering frontier for ruggedized electronics packaging. The need for alternative high temperature materials such as Phthalonitrile-based polymers has been on the rise to substitute the epoxy counterparts which have limited progression for such harsh environment applications. Resorcinol-based phthalonitrile (PN), known for their high thermal stability and good mechanical properties, can be a good candidate. However, investigations of PN as a microelectronics packaging material have not been substantial. Moreover, addition of fillers as well as the different filler types can alter the properties of PN such as its thermal behavior. This study looks into how alumina fillers affect the dielectric property, bulk resistivity and thermal conductivity of PN, which provides an insight of using PN as an encapsulation material for high temperature applications.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123140948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Image Detail Enhancement via Constant-Time Unsharp Masking","authors":"Dat Ngo, B. Kang","doi":"10.1109/EPTC47984.2019.9026580","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026580","url":null,"abstract":"Image degradation due to weather phenomena and poor lighting conditions is inevitable in photography and computer vision applications. For example, fine details like distant objects or traffic signs are easily obscured by haze, mist, or dust in the atmosphere. Thus, the proposed algorithm is designed to address this issue by means of unsharp masking technique. Our approach differs from other unsharp masking methods in: i) the ability to control the contribution of sharpness enhancement according to the local variance of the image, and ii) the constant-time algorithmic complexity by virtue of the constant-time O(1) box filter. The use of the image's local statistics allows the proposed method to add more details in the heavily-degraded areas and little or no details in the smooth areas. In addition, the advantage of speed facilitates the integration into real-time processing applications. A comparative study and quantitative evaluation are conducted with a state-of-the-art algorithm to demonstrate the performance and efficiency of the proposed approach.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123195879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Superconducting TiN through-silicon-vias for quantum technology","authors":"K. Grigoras, S. Simbierowicz, L. Grönberg, J. Govenius, V. Vesterinen, M. Prunnila, J. Hassel","doi":"10.1109/EPTC47984.2019.9026646","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026646","url":null,"abstract":"Through-silicon vias (TSVs) can be used to route signals and to obtain effective grounding in microwave circuits. The coating of the TSVs with a superconducting material is a challenge because of the high aspect ratio of the structures. In this paper, we present successful fabrication of superconducting $60 mu mathrm{m}$ diameter TSVs, coated by atomic layer deposition (ALD) of titanium nitride. The critical temperature Tc is approximately 1.6 K.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121478823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Co-Design of High-Isolation Chip-Package-Board in eWLB Package for 77 GHz Automotive Radar Application","authors":"Chuanming Zhu, Zongming Duan, Yan Wang, Ying Liu, Yuefei Dai","doi":"10.1109/EPTC47984.2019.9026665","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026665","url":null,"abstract":"This paper presents a co-design of 76-81 GHz chip-package-board based on embedded wafer level ball grid array (eWLB) package. The layout features of chip, package, and board are necessary considered and modeled since many electromagnetic couplings among them exist, especially at high frequencies. By means of accurate electromagnetic modeling, some unanticipated couplings can be considered in EM model. The designed chip containing 3-transmit channels and 4-receive channels is based on TSMC 65-nm CMOS general-purpose technology and flip-chipped on printed-circuit board (PCB). Low insertion loss and wide impedance matching are realized by carefully designing redistribution layer (RDL) in eWLB package and the grounded coplanar waveguide (GCPW) line on PCB. In addition, by properly designing the loaded stubs of RDL, the isolation level between phased-array channels is obviously improved with almost no effects on transmission responses. The result paves the way for high isolation, and cost-effective systems for 77-GHz automotive radar application.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126802093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Si-based Hybrid Micro-cooler Fabrication Process Development","authors":"Lau Boon Long, Han Yong, Zhang Xiaowu","doi":"10.1109/EPTC47984.2019.9026681","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026681","url":null,"abstract":"In this paper, silicon substrate wafer level fabrication process of liquid cooling microchannel is introduced. Fig. 1 shows the microchannels fabricated on the silicon wafer surface. This microchannel component is to be integrated into a heat sink package served as an advance liquid cooling solution for high power server electronics cooling. Sambhaji [1] suggested liquid microchannel cooling method as more effective, reliable and lesser mechanical vibration to draw intense heat flux from high power electronic devices; compared with conventional air-flow convection cooling. Nicholas [2] illustrated micro structure jet impingement onto mirco-porous structure to eliminate flow instabilities, meeting high heat dissipation from concentrator photovaltics devices. Hence, novelty of multi-layers microchannel fabrication becomes the key to meet these requirements. This paper demonstrated using silicon wafer level process to build the main components of microchannels, micro-fins and jet impingement-nozzles. Fig. 2 shows these three main key components fabrication on silicon substrate. These structures were fabricated through silicon deep reactive ion etching process. Key process parameters were developed and optimized to meet structural dimensions control limits, uniformity and surface roughness conditions. Additional dielectric layers were added before the lithography patterning for silicon-etch to ensure smoother etched surface achieved after long process time of plasma etching process. Optimized proportion ratio of dielectric layers and photoresist layers thickness were evaluated to meet the plasma etching selectivity requirement between the silicon, dielectric and photoresist materials. The remainder oxide layer on the silicon surface is critical acting as an adhesive layer for subsequent metallization process. Liquid chemical etching process was used to remove the photoresist layer after silicon plasma etching. The key challenge within the fabrication process flow is to perform double sided silicon micro-structures fabrication. Silicon substrate as a carrier wafer to temporarily bonded on the microchannel surface in order to perform silicon etching process on the others side of wafer. Bonding materials and conditions were evaluated in order to ensure no delamination and breaking of silicon substrate during the silicon plasma etching on “structured” substrate. Optimized process flow was developed as well to ensure there is no penetration of chemicals and gas onto the bonding surface which could deteriorate the materials properties, consequently failed to debond or broken during the debonding process after the silicon plasma etching process completed. Metalization process was introduced to deposit eutectic bonding layers on the microchannel surfaces. Process flow sequences and conditions were established to ensure good bonding quality between the components layers without liquid leakage. Experimental flow test was carried out. This shows good pressure d","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116604754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Aspect Ratio (>10:1) Via-Middle TSV with High-k Dielectric Liner Oxide","authors":"K. Chui, I-Ting Wang, Faxing Che, L. Ji, Zhu Yao","doi":"10.1109/EPTC47984.2019.9026683","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026683","url":null,"abstract":"Downward scaling of TSV feature-size provides benefits in terms of increased interconnection density, which translates to increased data bandwidth between devices/chips at both ends of the TSVs. However, there is little motivation in the reduction of TSV depth. As a result, the aspect ratio of TSV increased as its critical dimension (CD) decreases. In cases where the TSV CD becomes too small, deposition of the liner oxide becomes a critical issue. A thicker layer is needed to ensure sufficient coverage at the TSV bottom but there is a risk of the TSV opening closing up when the deposited layer is too thick. Atomic Layer Deposition (ALD) process offers excellent coverage and a higher dielectric constant with respect to silicon dioxide. This paper evaluates the use of ALD high-k dielectric (HfO2 and Al2O3) as an alternative for TSV liner.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124448556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Factors Impacting Bump Solder Extrusion, Failure Mechanism and Methodologies to Improve","authors":"Anandan Ramasamy, I. Singh, Shin Low, B. Lin","doi":"10.1109/EPTC47984.2019.9026656","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026656","url":null,"abstract":"Flip chip market is driven by the imminent need for circuit miniaturization, growth in internet of things, big opportunities in data centers and technological superior packaging. With the never ending need for smaller form factors and more & more IOs, bump pitches are getting smaller and smaller. Flip chip packaging with denser and smaller bumps in big packages becomes a challenge. Number of thermal processes also increases in flip chip processing. High layer count substrates added more stress to the bumps and the underfill material supporting the bumps. Bumps are the interconnect between the die and the organic substrate. Bumps are covered by underfill material in order to support the bumps mechanically and also to prevent solder extrusion. Bump solder extrusion is one of the challenging failures to overcome during processing and in the field application. Solder extrusion can happen due to underfill cracks or polyimide (PI) cracks or there is a delamination between underfill and PI, which is coated on the die surface. If the bonding strength between underfill and PI is weak, it can delaminate due to thermo-mechanical stresses during processing or in the field applications. This paper discusses critical factors which impact the adhesive strength between underfill and PI layer, the inputs and parameters required for critical factors and the results.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124216101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Silicon Optical Electrical Interposer - Fiber to the Chip","authors":"Lim Teck Guan, L. Yu, Jong Ming Chinq, Eva Wai Leong Ching, C. Choong, Lim Soon Thor, T. Ang, Ong Jun Rong","doi":"10.1109/EPTC47984.2019.9026602","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026602","url":null,"abstract":"A Silicon Optical Interposer for 2.5D integration of high speed electrical and optical circuit is proposed here. The Si Interposer functions as a base substrate for the optical alignment of the Photonic IC and the fibers which are held in a Si Fiber Block or can be integrated directly. The alignment scheme is semi passive, it utilizes a set of U-grooves with submicron accuracy and the cylindrical face of a pair of precision pin for the self-alignment. The Photonic IC and the Fiber Block are faced down assembled on the Si Interposer. Electrical connections are made using the flip chip micro bumps between the Photonic IC and the Si Interposer. The number of channel in this proposed design is scalable and is applicable for high speed optical transceiver design.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132113634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Yield Impacting Defects and Prevention of Microbump Formation","authors":"Qin Ren, Hongyu Li, M. Kawano","doi":"10.1109/EPTC47984.2019.9026698","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026698","url":null,"abstract":"Microbumping is one of key technologies for enabling 3D integration of semiconductor devices. Microbump based interconnect joining allows silicon dies with through-silicon vias (TSVs) to be stacked on each other [1]. Along with high level of integration, bumping process becomes more and more challenging. In this paper, some yield impacting defects during microbump fabrication are detected, root causes of these defects are discussed and analyzed. Prevention methods for these defects were proposed and demonstrated. With these defect prevention methods, yield can be enhanced without substantial increase in processing cost.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132042014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}