Si-based Hybrid Micro-cooler Fabrication Process Development

Abstract

In this paper, silicon substrate wafer level fabrication process of liquid cooling microchannel is introduced. Fig. 1 shows the microchannels fabricated on the silicon wafer surface. This microchannel component is to be integrated into a heat sink package served as an advance liquid cooling solution for high power server electronics cooling. Sambhaji [1] suggested liquid microchannel cooling method as more effective, reliable and lesser mechanical vibration to draw intense heat flux from high power electronic devices; compared with conventional air-flow convection cooling. Nicholas [2] illustrated micro structure jet impingement onto mirco-porous structure to eliminate flow instabilities, meeting high heat dissipation from concentrator photovaltics devices. Hence, novelty of multi-layers microchannel fabrication becomes the key to meet these requirements. This paper demonstrated using silicon wafer level process to build the main components of microchannels, micro-fins and jet impingement-nozzles. Fig. 2 shows these three main key components fabrication on silicon substrate. These structures were fabricated through silicon deep reactive ion etching process. Key process parameters were developed and optimized to meet structural dimensions control limits, uniformity and surface roughness conditions. Additional dielectric layers were added before the lithography patterning for silicon-etch to ensure smoother etched surface achieved after long process time of plasma etching process. Optimized proportion ratio of dielectric layers and photoresist layers thickness were evaluated to meet the plasma etching selectivity requirement between the silicon, dielectric and photoresist materials. The remainder oxide layer on the silicon surface is critical acting as an adhesive layer for subsequent metallization process. Liquid chemical etching process was used to remove the photoresist layer after silicon plasma etching. The key challenge within the fabrication process flow is to perform double sided silicon micro-structures fabrication. Silicon substrate as a carrier wafer to temporarily bonded on the microchannel surface in order to perform silicon etching process on the others side of wafer. Bonding materials and conditions were evaluated in order to ensure no delamination and breaking of silicon substrate during the silicon plasma etching on “structured” substrate. Optimized process flow was developed as well to ensure there is no penetration of chemicals and gas onto the bonding surface which could deteriorate the materials properties, consequently failed to debond or broken during the debonding process after the silicon plasma etching process completed. Metalization process was introduced to deposit eutectic bonding layers on the microchannel surfaces. Process flow sequences and conditions were established to ensure good bonding quality between the components layers without liquid leakage. Experimental flow test was carried out. This shows good pressure drop trend with increasing flow rate without leaking and blockage issue during the test. Experimental test show good repeatability results and illustrated good reliability results of the silicon microchannel samples.