2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Printing Process of Electrically Conductive Silver on Heat Transfer Polymer Substrates for Wearable Electronics Applications","authors":"B. Salam, Z. Cen, X. Shan, B. Lok","doi":"10.1109/EPTC47984.2019.9026604","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026604","url":null,"abstract":"Most of textile substrates are porous because they are fabricated from yarns by weaving, or knitting. Hence direct printing of electrically conductive ink to form solid patterns on textile fabrics is a challenge. One of the conductive circuitry forming methods includes the usage of the heat transfer polymer (HTP) substrate. In this study, we investigate the described fabrication process which includes the printing of electrically conductive silver ink on the HTP substrate for wearable electronics applications. The printing process on the HTP substrate using screen printing was empirically studied using our newly developed roll-to-roll pilot line for flexible hybrid electronics. The investigated materials included $60mu mathrm{m}$ thick HTP substrates, and a shear thinning silver ink. The test vehicles includes lenticular patterns from 200 to $700mu mathrm{m}$. The results of the study show that the different line-widths towards the resistivity values of the same length printed silver patterns follow a power function equation. The study also finds that the average electrical resistance values of the printed silver on the HTP substrate are 17.3% lower than those of on the polyethylene terephthalate (PET) substrate.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Accelerated Thermal Cyclic Loading on Structural Reliability of Cu-filled TSV","authors":"D. Sonawane, Praveen Kumar","doi":"10.1109/EPTC47984.2019.9026640","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026640","url":null,"abstract":"Through Si Via (TSV) has emerged as one of the promising technologies for the 3D integration of the microelectronics packages. However, difference in the coefficient of the thermal expansion of Si and Cu leads to generation of large thermal stresses in these structures when subjected to thermal excursions either during post fabrication processes or service period due to on-off cycles of device. In here, accelerated thermal cycling tests were carried out in the temperature range of −50 to 150°C with two different heating cooling rates on the TSV samples. It was observed that slow heating-cooling cycling causes extrusion of few Cu grains near the Cu-Si interface which was not observed when samples were subjected to the fast-thermal cycling. Also, at few locations along the interface, Cu-Si reaction occurrence signs were observed. Finite element analysis (FEA) which was performed to gain more insights into the experimental results suggests that creep strain accumulated near interface of Cu-Si was higher in the magnitude in case of the slow thermal cycling compare to the faster one. From the stress measurement using the FEA, it was also understood that the Cu-Si interface gets subjected to large stresses during thermal cycling. Therefore, it can cause the degradation of the diffusion barrier layer and can pave the pathway for the Cu-Si reaction to happen.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"2673 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125378017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Considerations on Integration of Through Silicon Via with 3D NAND Scaling","authors":"Mei-chien Lu","doi":"10.1109/EPTC47984.2019.9026685","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026685","url":null,"abstract":"Recent advancements in data storage technology have been driven by strong demands in applications in high performance computing, artificial intelligence, enterprise storage, internet of things (IoT), and mobile applications. Flash memory has migrated to 3D NAND in the past five years leveraging atomic layer deposition and plasma etching to overcome lithography scaling limitations. The 3D NAND implementation has increased memory cell density and reduced chip sizes, but also faces another technology pivot in continuous layer scaling. To further increase bandwidth, through silicon via (TSV) interconnect technology is considered for 3D NAND. In addition to typical TSV integration, the process and device complexity of 3D NAND memory array structures is briefed for its increased risks of TSV integration with 3D NAND chips. Analysis is then conducted for chip stacking using TSV integration compared against wirebond chip stacking on performance, power, area and cost. The power consumption reduction and performance improvement by adoption of TSV technology have trade-offs on chip size increase, yield loss, cost increase, and time-to-market risk increase. The implementation of TSV technology on packaging of stacked 3D NAND chips is therefore deemed to be application oriented decision. This study will also present surveyed results in recent patent filings in 3D NAND and TSV areas since 2014. As the industry continues to face challenges and higher expectations, alternative package architectures are explored for discussions.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125484993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Failure Mechanism Study for Low-k Device Bond Pad Crack Post Temperature Cycle","authors":"Haiyan Liu, Xingshou Pang, Sean Xu","doi":"10.1109/EPTC47984.2019.9026597","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026597","url":null,"abstract":"Copper (Cu) wires are increasingly used in semiconductor devices to provide cost-effective packaging. Many of the challenges for Cu wire have been evaluated to meet the stringent quality requirements, especially for automotive applications. The reliability requirement for automotive devices are more stringent than others. The wafer technology used in this study was CMOS40, with an Al thickness is 28KA and a 53um pad opening and the package studied was a MAPBGA. The failure mode during ATE test is OPEN fail post temperature cycling and was associated with delamination at the bond pad interface. Contamination was not observed at the delaminated interface. Closer visual inspection showed the die attach fillet was high on the side wall of the 7-mil die in the same area as the failed pins. Mechanical simulation was done to investigate the failure mechanism. The result showed that high die attach fillet can cause higher stress and delamination that can lead to Cu ball failure during temperature cycling. The simulation showed an exponential drop in the energy release rate as the fillet height decreased. Lowering of the filet height on the die edge and making it more uniform was done by optimizing the die attach epoxy dispense pattern. Electrical test was performed on the assembled parts at T0, post MSL3/260C, and post 700 temperature cycles (−55°C to 150°C). After filet height optimization, all units pass electrical test with no failures.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129794707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A method to test millimeter wave antenna in package over the air by using orthogonal signals for production throughput enhancement","authors":"Bo-Siang Fang, Kuan-Ta Chen, Cha-Chu Lai, Y. Lu, Cheng-Tsai Hsieh, W. Liang","doi":"10.1109/EPTC47984.2019.9026630","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026630","url":null,"abstract":"The design of the millimeter wave antenna in package (AiP) or antenna in module (AiM) makes testing over the air a must. Because of the long test time and the use of the anechoic chambers, a high-efficiency parallel measurement must be performed in mass production. We propose to use the orthogonal signals to divide the measurement groups, just like the concept of Code Division Multiple Access (CDMA) communication system, but we modify the signal process of baseband to optimize the accuracy of power measurement. As a result, the uncertainty of the measurement can be below 0.1dB even when the interference from the other measurement group is 20dB higher than the test signal. Compared with the traditional test methods, the proposed method can save equipment expenditure and improve test throughput.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130816150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assessing of Wire Bonding on Gold Plated Pads on Epoxy Mold Compound Wafer","authors":"L. Wai, D. Ho","doi":"10.1109/EPTC47984.2019.9026571","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026571","url":null,"abstract":"Epoxy mold is one of the materials being used in Fan-out Wafer Level Packaging (FOWLP). It is challenging to wire bond on epoxy mold compound wafer which the mold materials property is less stiff at high temperature if compare to silicon wafer. In this study, it has been using the reference bonding parameters from blanket Aluminium silicon chip to bond on gold pad on epoxy mold compound wafer. The reference bonding parameters could not be repeated on the epoxy mold compound wafer especially for copper wire. Nonstick on pad were seen. The bonding parameters required to stick the copper wire on the bond pad is far away different from the reference parameter. The wire pull readings were collected from the epoxy mold compound wafer after the wires were successfully bonded continuously. Wire pull readings of average 5.427gf was achieved for Au wire and average of 5.99gf for palladium-coated copper core wire. After 150DegC baking for 96hours, the wire pull average is 5.24gf and ball shear average is 21.65gf. Average wire pull of 6.32g and average ball shear of 29.69gf was achieved after 175DegC baking for 96 hours. In generally, all wire pulls >3gf.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117097529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Insights into Growth Behavior of Intermetallic Compounds in Sn-Ag-Cu Solder Joints during Mechanical and Thermo-Mechanical Deformation Processes","authors":"Anwesha Kanjilal, Praveen Kumar","doi":"10.1109/EPTC47984.2019.9026611","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026611","url":null,"abstract":"This work focuses on understanding the effect of strain rate imposed during various thermo-mechanical excursions (TMEs), such as thermal cycling and creep, and isothermal aging on the extent of coarsening of intermetallic compounds (IMCs) in diffusion bonded Sn-Ag-Cu(SAC)/Cu solder joints as well as reflowed bulk solder alloys. Fabricated samples were subjected to isothermal aging (IA), creep, thermal cycling (TC) and thermo-mechanical cycling (TMC) and the microstructure coarsening was monitored at regular intervals. A comparison has been made between thick joints of 1 mm thickness and micro-scale joints having a thickness of $sim 150 mu mathrm{m}$. Both the interfacial IMC layer and the Ag3Sn precipitates in the bulk are observed to undergo significant coarsening during each of the TMEs. While the $150 mu mathrm{m}$ joint showed a faster growth in the IMC layer thickness as compared to 1 mm joint in the initial stages, a drastic reduction in the layer thickness was also observed in both the joints in the latter stages. Such a behavior is believed to happen due to the breaking of the IMC layer into the solder, a phenomenon which can severely impact the reliability of the joint. It is also observed that cyclic shear strain rates have the maximum severity on the microstructure coarsening kinetics for all joint sizes. Finally, a comprehensive understanding of the effect of all the TMEs on the coarsening behavior and joint reliability is proposed.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"4 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114110662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental Analysis of Novel Triple Fluid Heat Exchanger for Hybrid Cooling Application","authors":"N. Kuppusamy, Lee Poh Seng, Daryl Koh Chong Wei","doi":"10.1109/EPTC47984.2019.9026567","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026567","url":null,"abstract":"This papers focuses on experimental analysis of novel Triple Fluid Heat Exchanger (TFHEX) to manage heat from hybrid cooled servers. TFHEX is a finned double tubed heat exchanger that consists of two types of liquid (hot water and warm water) and one gas (hot air). The hot air flows through the fins and the hot water flows through the inner tube. The cooling water that flows through the annular tube removes heat from both hot air and hot water. The prototype model of TFHEX is tested in wind tunnel at different heat load. The heat load is varied by varying the flow rate at a given inlet fluid temperature. The overall performance of the heat exchanger is presented in terms of heat transfer efficiency over the flow rate. The experimental results were also compared with analytical results. While there is some deviation between analytical and experimental results, the results promises that TFHEX can dissipate heat from different fluids at various ratio which necessary customization and this heat exchanger suitable for high ambient data center application.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122310749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimizing ODT condition and Driver's turn-on resistance to achieve SI of LPDDR dual rank configuration","authors":"Heeseok Lee, Jisoo Hwang, Hoi-Jin Lee","doi":"10.1109/EPTC47984.2019.9026595","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026595","url":null,"abstract":"Increasing the clock frequency of IO system with LPDDR4 and LPDDR5 in SOC (system on a chip) has escalated the importance of SI on the functional stability and low power operation of the circuit blocks, because the challenge to design and verification of SDN (signal delivery network) of SOC, DRAM and system-level PCB is rising higher and higher with limited cost budget and design cycle-time. Therefore, SDN design should include the proper channel design satisfying signal loss and adequate cross-talk, as well as proper ODT scheme with optimum turn-on resistance of driver. In this work, a design methodology to achieve signal integrity up-to 6.4Gbps/pin dual rank system with LPDDR DRAM and DRAM controller has been presented based on frequency-domain approach with voltage transfer function. It has been demonstrated that optimizing ODT condition of target and nontarget terminal and turn on resistance of Tx (transmitter) is achieved before time-domain simulation which generally requires huge computation time.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127467612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability of Substrate Embedded Rectifiers for High Voltage Applications","authors":"K. Meier, J. Meyer, F. Schein, D. Sirkeci, A. Ostmann, E. Oertel, H. Westphal, K. Lang, K. Bock","doi":"10.1109/EPTC47984.2019.9026672","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026672","url":null,"abstract":"As of today, various solutions to handle the dissipating heat of power electronics devices are available. These include the application of heatsinks, overmolding, embedding of components into substrates, use of substrates with embedded metal or ceramic heatsinks or liquid cooling approaches. When it comes to power electronics for high voltages and fast switching the parasitic capacity has to be considered. This parasitic capacity affects the electrical performance and may finally even lead to damage of the device. Embedding of metal heatsinks or mounting a substrate to a metal heatsink can even increase the parasitic capacity and hence, worsen the scenario. In this project a rectifier had to be built suitable for voltages of up to 20 kV and switching frequencies of 100 kHz while achieving a low parasitic capacity of max. 3 pF. High voltage diodes were selected to meet the electrical requirements. To fullfil both the thermal and capacitance demands the diodes were embedded into a substrate made from a highly thermal conductive FR4 material. In addition, the substrate is mounted to a ceramic heatsink to enable a superior cooling but to limit the parasitic capacity at the same time. This setup was characterised for its thermal management behaviour in the as build state. Though the lamination of the substrate to the ceramic heatsink showed some challenges its cooling performance could be assessed. Subsequently, the system without the ceramic heatsink was exposed to temperature shock cycles at −40/+125°C for up to 2,000 cycles to analyse the long term stability of the system behaviour. For the repeated investigation of the thermal behaviour and the structural integrity of the system a novel analysis approach using an infrared camera was applied. Cross sections were done in addition to verify the results from the novel thermal analysis approach. As of now no thermo-mechanical damage of the rectifier could be observed proving the ability of the embedding approach and the validity of the results gained with the novel non-destructive analysis approach.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"4 S1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133203617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}