Considerations on Integration of Through Silicon Via with 3D NAND Scaling

Abstract

Recent advancements in data storage technology have been driven by strong demands in applications in high performance computing, artificial intelligence, enterprise storage, internet of things (IoT), and mobile applications. Flash memory has migrated to 3D NAND in the past five years leveraging atomic layer deposition and plasma etching to overcome lithography scaling limitations. The 3D NAND implementation has increased memory cell density and reduced chip sizes, but also faces another technology pivot in continuous layer scaling. To further increase bandwidth, through silicon via (TSV) interconnect technology is considered for 3D NAND. In addition to typical TSV integration, the process and device complexity of 3D NAND memory array structures is briefed for its increased risks of TSV integration with 3D NAND chips. Analysis is then conducted for chip stacking using TSV integration compared against wirebond chip stacking on performance, power, area and cost. The power consumption reduction and performance improvement by adoption of TSV technology have trade-offs on chip size increase, yield loss, cost increase, and time-to-market risk increase. The implementation of TSV technology on packaging of stacked 3D NAND chips is therefore deemed to be application oriented decision. This study will also present surveyed results in recent patent filings in 3D NAND and TSV areas since 2014. As the industry continues to face challenges and higher expectations, alternative package architectures are explored for discussions.