面内特性变化对有机衬底翘曲形状的影响

S. Kohara, K. Okamoto, H. Mori
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引用次数: 1

摘要

减少有机衬底的翘曲是倒装芯片封装应用中的挑战之一,因为翘曲会影响芯片连接的可制造性,并可能影响焊点的可靠性。有机衬底的机械模拟结果在反映电路图案的对称性翘曲形状,通常在碗形状,当电路图案被考虑在内。然而,实际制造的基板经常表现出随机扭曲的翘曲形状,并且即使它们具有相同的电路设计模式并且从同一面板分割,也彼此不同。翘曲形状传播的潜在原因是制造过程中的工艺或环境条件的不均匀性,这可能导致基材性能的面内变化或波动。本文采用力学模拟的方法分析了有机衬底在衬底性能面内变化下的变形。采用平面铜和核心层两侧有绝缘介质层的简单衬底结构作为分析模型。势变性能是指材料的弹性模量和热膨胀系数等性能。诸如层厚度之类的形状因素也可以沿平面内方向变化。在我们的分析中,平面内的变化作为一个整体被纳入模拟作为绝缘介质层的固化收缩率的变化,以产生各种翘曲形状。在有限元模拟中,由于固化收缩率与温度无关,因此采用了固化收缩率。与基底尺寸的横向长度尺度的线性变化被应用。通过改变固化收缩率最大值的位置,研究了几种形态的变化。分析表明,变形的形态是决定衬底翘曲形状的重要因素。分析还表明,衬底前后层之间的性能平衡对翘曲形状的决定有很大的影响。平面内层厚变化分析表明,绝缘介质层的翘曲幅度大于导电层。结果表明,控制绝缘介质层的性能均匀性和厚度对于减少制造过程中由于性能不均匀而引起的翘曲是非常重要的。对具有3-2-3堆积层结构的测试基板进行了面内性能变化的翘曲分析,以考察面内性能变化对图案基板翘曲的影响。结果表明,当具有对称电路图案的衬底发生不对称的面内特性变化时,衬底的翘曲会导致不对称的形状。电路图样引起的翘曲与面内特性变化引起的翘曲重叠。这表明,通过在电路设计中应用适当的补偿,具有已知非均匀性趋势的基板可以减少翘曲。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Effects of in-plane property variations on warpage shapes of organic substrates
The reduction of warpage of organic substrates is one of the challenges in flip chip package applications, since the warpage affects the manufacturability of chip joining and potentially, the solder joint reliability. Mechanical simulation of organic substrates results in a warpage shape that reflects the symmetry of the circuitry pattern, often in a bowl shape, when the circuitry pattern is taken into account. However, the actual substrates manufactured often exhibit warpage shapes that are randomly distorted and are different from each other even when they have identical circuitry design patterns and are segmented from the same panel. Potential causes for the spread in warpage shapes are inhomogeneities in processes or environmental conditions during manufacturing which can lead to an in-plane variation or fluctuation in substrate properties. In this report, the deformation of organic substrates under in-plane variations of substrate properties are analyzed by mechanical simulation. A simple substrate structure with a plane copper and an insulating dielectric layer on both sides of the core layer was used as the model for the analysis. Potential varying properties are material properties such as elastic modulus and coefficient of thermal expansion. The form factors such as layer thicknesses can also vary along the in-plane direction. In our analyses, the in-plane variations as a whole are incorporated in simulation as a change in cure shrinkage rate of insulating dielectric layers in order to generate various warpage shapes. The cure shrinkage rate was used, since it is temperature independent in simulations by finite element method (FEM). Linear variations with lateral length scales of the substrate size are applied. Several configurations of variations are studied by changing the positions of maximums of the cure shrinkage rate. The analyses revealed that the configuration of variations is an important factor in determining the warpage shape of a substrate. The analysis also showed that the balance of property between front layers and back layers of the substrate has a great influence in determining the warpage shapes. The analysis of the in-plane layer thickness variation showed that the magnitude of warpage for insulating dielectric layer is greater than that for the conductive layer. The result suggests that the control of the uniformity of properties and thickness of insulating dielectric layers are important in reducing the warpage caused by inhomogeneity of properties occurring during manufacturing processes. The warpage analysis of the in-plane property variation was also conducted for a test substrate with a 3-2-3 build-up layer structure to examine the effects of in-plane property variation on warpage of patterned substrates. The results showed that the warpage of a substrate with a symmetric circuitry pattern results in an asymmetric shape when an asymmetric in-plane property variation occurs. The warpage caused by circuitry pattern overlaps with that caused by in-plane property variation. It suggests that the reduction of warpage is possible for the substrates with properties of known trends in inhomogeneity by applying an appropriate compensation in the circuitry design.
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