2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Comprehensive Design and Analysis of Fan-Out Wafer Level Package","authors":"Xiaowu Zhang, Y. Andriani, M. C. Jong, L. Bu, B. L. Lau, Simon Lim Siak Boon, Sharon Lim Pei Siang, Yong Han, Songlin Liu, Xiaobai Wang","doi":"10.1109/EPTC47984.2019.9026620","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026620","url":null,"abstract":"This paper presents an advanced modeling technology on wafer warpage after post mold curing (PMC) for the 12 inch mold-1st Fan-Out Wafer Level Packaging (FOWLP) with consideration of effects of viscoelastic model and chemical cure shrinkage, and layer design of the mold-1st packages. Results show that warpage of mold-1st FOWLP wafer predicted by the advanced modeling technology agrees well with the experimental result. A new guideline for FOWLP process flow is provided as well, which will be useful to the packaging industry. The advantages of the new guideline for FOWLP process flow are: (1) to eliminate wafer warpage correction process and save a lot of cost and time; (2) to serve as a basis for process selection to meet the trends and needs of a reliable fan-out wafer level package with lower wafer warpage during FOWLP wafer process; and (3) to be important to enhance survivability during wafer process and thin-wafer handling.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122670104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Innovative Packaging Solutions of 3D Integration and System in Package for IoT/Wearable and 5G Application","authors":"Frank Lian, Davidlion Wang, Ryan Chiu, Jase Jiang, Yu-Po Wang","doi":"10.1109/EPTC47984.2019.9026573","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026573","url":null,"abstract":"Along with the rapid spread of portable electronic products on the mobile computing market, the increase in the use of video streaming, photo sharing and also other data-intensive applications keep growing up continuously for now. More and more IoT/Wearable and 5G connectivity devices are required with Radio Frequency (RF) and Front-End Module (FEM) which has driven the development of IC packaging towards on small form factor, thin profile, better electrical and thermal performance, as well as 3D stacking for multi-function integration [1]. To approach these requirements, the System in Package (SiP) can be a combination of one or more chips plus optionally passive components by using Surface Mount Technology (SMT) and 3D structure of double side into a single package to offer a small form factor, high performance and systemization implemented. The high speed SMT process accomplishes the high-density with more than 50 discrete passive as well as active components and heterogeneous integration on package level approach. The development of double side technology offers the advantage of package size shrinkage by the same integrating discrete passive and active components layout. In this paper, the innovative packaging solutions of 3D double side SiP including the platform for both strip form of substrate base and wafer form of Fan-Out Redistribution Layer (RDL) base will be well introduced. Fan-Out RDL is an extension approach of Wafer Level Chip Scale Package (WLCSP), this technology is different from conventional wire bond or flip chip packages because the redistribution dielectrics and fine-line plated conductors are used for interconnection to replace the packaging substrates. As a case study, the calculation of 3D SiP package size can be shrunk around 50% area and the total package thickness can achieve around 15% z-height reduction with thin form coreless substrate and Fan-Out RDL technology utilization. The characterization analysis will apply simulation methodology for electrical comparison on DC resistance and parasitic inductance, thermal comparison on Theta JA (°C/W) and warpage comparison on the package structure of 3D double side SiP. Also, the typical reliability testing (Temperature Cycle Test, High Temperature Storage Life Test, Unbiased High Accelerated Stress Test) are built to verify 3D double side SiP structure for future IoT/Wearable and 5G devices application. Currently the market trends clearly drive towards 3D double side SiP, so this article illustrates the innovative packaging solutions with both substrate base and Fan-Out RDL base to provide a unique opportunity for enabling 3D integration and system in package.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"49 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120873872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Construction Kit of RF-Blocks in Package Technologies","authors":"Fabian Hopsch, R. Trieb, A. Heinig","doi":"10.1109/EPTC47984.2019.9026858","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026858","url":null,"abstract":"Advanced packages are necessary to cope with the requirements of 5G and radar technologies with 60 GHz and beyond. For proper RF design with rising package technology requirements demands for usage of predefined structures with predefined layout elements, manufactured and measured elements. This paper deals with an approach to have such elements available to build advanced types of packages in shorter time compared to classical approaches. The approach is a general approach but it is demonstrated with an advanced two-level package-on-package technology with a leading edge IC technology. It is also used explain the build-up of a construction kit of RF-blocks from the design phase of test structures up to measurement of such structures, qualification and model building. From the test structure more general structures can be derived and used in the design of future 5G applications. This enables better time-to-market, reduces cost and provides higher design validation in terms of first time right.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121468810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of trench ground structures for cross talk reduction in high speed single ended bus","authors":"Mihai D. Rotaru, B. E. Cheah, J. Kong","doi":"10.1109/EPTC47984.2019.9026674","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026674","url":null,"abstract":"The near-end cross talk in high speed single ended bus configuration can have a negative effect of signal integrity. In this work a 3D trench on the reference plane is used to reduce the near-end cross talk in single ended bus. The electromagnetic principle behind the positive effects of the 3D trench ground are discussed and explained here. Also, the measurement results obtained for the fabricated test boards are presented showing a reduction of up to 40% in the near-end cross talk for the single ended bus routed above the 3D trench. Two different 3D trench designs are presented, and their advantages and limitations are discussed.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129602367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on Through Silicon Via (TSV) filling failures on various electroplating conditions","authors":"Gilho Hwang, R. Kalaiselvan, M. I. E. Sam, Hsiao Hsiang-Yao","doi":"10.1109/EPTC47984.2019.9026599","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026599","url":null,"abstract":"TSV Cu filling failures in different electroplating condition were studied. Constant current electroplating was used for 5um x 50um and 10um x 100um TSV Cu filling. We investigated output voltage of defect-free TSV and TSV with defect to understand the different Cu growth behavior. Agitation during electroplating affects the range of applicable electroplating current. Compared to electroplating with agitation, higher current can be applied for 10um x 100um TSV without agitation while lower current for 5um x 50um TSV has Cu filling failure. Voltage variation during electroplating reveals the competitive adsorption of additives. Initial voltage drop is strongly related to TSV Cu filling failure.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131057278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Magnetic Inductor Integration in FO-WLP using RDL-first Approach","authors":"Soh Siew Boon, D. Wee, Raju Salahuddin, R. Singh","doi":"10.1109/EPTC47984.2019.9026624","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026624","url":null,"abstract":"FO-WLP with integrated solenoidal magnetic core inductor in the RDL layer was proposed and developed in this work. This provide a packaging solution to integrate high performance inductors for high efficiency power conversion to the embedded device chips without sacrificing valuable chip estate as compared to integrating the inductors on the surface of device chip. Two photo-dielectric materials were evaluated and it was found that material with higher tensile strength and percent elongation was able to sustain the magnetic film deposition and patterning process without showing cracks or delamination. Different patterning methods of the magnetic film were explored. Wet etching method has residue issues on low lying features in valley and contact vias. The sidewall of the magnetic core was highly sloped for thicker magnetic film due isotropic nature of the wet process. Dry etching was inefficient to etch the thick magnetic film. A new patterning method was developed to overcome the wet etching issues to produce magnetic core with vertical sidewall with no residue issues. Electrical characterization was performed on the fabricated inductor. The inductor shows a flat inductance response up to its self-resonance frequency, and a quality factor of 14 can be achieved. These indicates that the inductor has low-loss and can be utilized in high-efficient power conversion.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133466064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Optimization of Hollow Hybrid Fin Heat Sinks under Impinging Airflows","authors":"Nico Setiawan Effendi, Jeong-Sik Park, B. Kim, Kyoung-Joon Kim","doi":"10.1109/EPTC47984.2019.9026713","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026713","url":null,"abstract":"The study herein describes the design optimization of the hollow hybrid fin heat sink (HHFHS) using a numerically developed Nusselt number correlation. The hollow hybrid fin is a hollow pin fin with a perforation near the base and radially extruded plate fins. The correlation was based on the geometric and flow parameters of the HHFHS under impinging airflows. The optimization utilizes the correlation for hundreds of HHFHS geometric combinations of number of fins, fin diameter, plate fin width, and fin height. Two approaches are used for determining the optimal HHFHS design. One approach finds the lowest thermal resistance for the predefined range of the mass. The other approach is to multiply the thermal resistance and the mass to find the design parameters with the best mass-based performance.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130014222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Die Attachment on Bare Copper Surface by Non-Pressure Silver Sintering in Inert Atmosphere","authors":"Ly May Chew, Tamira Stegmann, Erika Schwenk, W. Schmitt","doi":"10.1109/EPTC47984.2019.9026669","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026669","url":null,"abstract":"Silver sinter material has been considered as a promising alternative die attach material for high-lead solder as it possesses excellent properties such as high melting temperature, high thermal and electrical conductivity. This paper focuses on the development of a safe-to-use micro-silver sinter paste (mAgic DA250) for non-pressure sintering on Cu surface in inert atmosphere as a possible drop-in solution for high-lead solder material. To be compatible to the present manufacturing process, this newly developed sinter paste is designed to be able to continuously dispense over 8 hours. We observed no missing pattern, tailing and needle clogging over 8 hours continuous dispensing. Ag metallized Si die was attached on bare Cu TO 220 lead frame by non-pressure sintering process in a convection batch oven. X-ray measurement was performed on the sintered samples showing that no void was formed in the sintered layer. An average die shear strength of 18 N/mm2 was achieved with the failure mode of cohesive break in the sintered layer. Silver sintered layer can be found on both the die backside and Cu lead frame surface after Si die was sheared indicating that strong adhesion was generated on both Ag and Cu surfaces. A rather dense sintered layer is strongly bonded onto Ag metallized die and Cu lead frame which is evidenced by cross-sectional SEM images. Additionally, the EDX result illustrates an interdiffusion of Ag and Cu occurring at the interface between silver sintered joint and Cu lead frame. Pressure cooker test with the test conditions of 121°C, 100% RH was performed for the unmolded sintered samples and a slight decrease in die shear strength from 18 N/mm2 to 15 N/mm2 was observed after 96 hours test demonstrating that the sintered joint can withstand the extremely high humidity condition. To study the effect of the paste storage conditions on the die shear strength, mAgic DA250 were stored separately in a freezer (−40°C) and a refrigerator (2-10°C) and subsequently used for nonpressure sintering process. A relatively similar die shear strength was obtained showing that mAgic DA250 sinter paste can be flexibly stored in either a freezer or a refrigerator.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114236805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of Copper/Dielectric Hybrid Fusion Bonding with Cavity for CMOS compatible Wafer Level Hermetic Packaging","authors":"A. Malainou, J. Visker, D. Tezcan","doi":"10.1109/EPTC47984.2019.9026626","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026626","url":null,"abstract":"Wafer level hermetic packaging is a requirement for many MEMS devices, eg. inertial sensors, to create a miniaturized and controlled environment. Typically, these MEMS devices are integrated with CMOS readout circuitry for high functionality. In this paper, we consider such a MEMS device which is built in a cavity Silicon-On-Insulator (C-SOI) wafer by dielectric patterning and deep Silicon etching (DSiE). MEMS device wafer is then hybrid fusion bonded to a CMOS wafer, electrically connected to the circuitry and hermetically sealed – i.e. wafer level packaged- at the same time (Fig. 1). To enable all these three functions at once, we developed and demonstrated a wafer level copper (Cu)/dielectric hybrid bonding below 400°C while the dielectric area is partly etched to create cavities. This work has been carried out on 200mm wafers in a CMOS compatible fab.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114597160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of Metal Distribution and Bonding Characteristics according to FAB Formation Conditions","authors":"Sangyeob Kim, SungMin Jeon, B. Jung, Seung-Hui Kim, J. Moon","doi":"10.1109/EPTC47984.2019.9026680","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026680","url":null,"abstract":"Several attempts have been made to lower the price of materials in the semiconductor market. Among them, the wire used for interconnection has a disadvantage of high material price in the field of using gold. Many packages have evolved to other technologies to improve performance and are moving away from wire bonding process, but many packages still use bonding wires. In the bonding wire market, in order to reduce prices, gold is being replaced by inexpensive copper, and now the market for copper wire coated with precious metals considering workability is dominant. [1], [5] However, due to the rigid nature of copper, packages with sensitive wiring structures are difficult to apply. [2] Silver alloy wire and noble metal coated silver wire have been developed to lower the wire price of these sensitive packages. [3] In the case of the recently developed noble metal coated silver wire, unlike a silver alloy bonding wire, a spherical ball shape can be realized without using inert gas when forming a Free Air Ball. Due to these advantages, it has recently been in the spotlight as a wire for replacing Au wire. [3] In this paper, experiments were conducted on the bonding conditions of silver wire coated with noble metals. The bondability of the prepared noble metal-coated silver wire according to the Free Air Ball formation conditions was verified. Specifically, evaluation was performed according to the current change at the time of Electronic Flame Off, the type of inert gas, and the size of the Free Air Ball. The evaluation confirmed the optimum bonding conditions for the application of the noble metal coated silver wire.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134490337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}