Development of Copper/Dielectric Hybrid Fusion Bonding with Cavity for CMOS compatible Wafer Level Hermetic Packaging

Abstract

Wafer level hermetic packaging is a requirement for many MEMS devices, eg. inertial sensors, to create a miniaturized and controlled environment. Typically, these MEMS devices are integrated with CMOS readout circuitry for high functionality. In this paper, we consider such a MEMS device which is built in a cavity Silicon-On-Insulator (C-SOI) wafer by dielectric patterning and deep Silicon etching (DSiE). MEMS device wafer is then hybrid fusion bonded to a CMOS wafer, electrically connected to the circuitry and hermetically sealed – i.e. wafer level packaged- at the same time (Fig. 1). To enable all these three functions at once, we developed and demonstrated a wafer level copper (Cu)/dielectric hybrid bonding below 400°C while the dielectric area is partly etched to create cavities. This work has been carried out on 200mm wafers in a CMOS compatible fab.