在探头中实现极低电压测试的研究

Yan Liu, Helen Li, Albert Zheng
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引用次数: 0

摘要

集成电路(IC)制造商通过生产测试来检测缺陷部件,以保证产品的质量水平。弱ic存在缺陷,这些缺陷在部分或全部正常工作条件下不会导致功能失效,但会降低ic的性能、降低噪声裕度或消耗过大的电源电流。目前普通的低电压测试不能缺陷弱集成电路或消除早期寿命故障。汽车和军用客户对质量要求非常高。极低压测试可以检测到导致早期失效或间歇性失效的缺陷(缺陷)。超低电压测试的成本也很低。极低电压测试是在远低于其标称工作电压的电源电压下进行测试的一种方法。它可以检测由降级信号或减小驱动门引起的电阻性短路和延迟缺陷。可在模具层面实现,不需要特殊的设备要求更换缺陷,不带来额外的成本。本文主要针对极低电压在探头级直流扫描试验中的实现进行了研究,讨论了不同域设置下直流扫描试验的核心电压值。JMP软件是本研究中使用的数据分析工具,包括DOM1、DOM2、DOM3和ARM内核之间的数据比较。优化了磁芯电压,确定了最佳的使用参数,并在探头程序中实现。收集了实际探头的极低压废品,并进行了电气和物理失效分析。对故障单元进行诊断、Level (VDD_SOC_CAP)与Period之间的shmoo分析、Laser Assisted Device change (LADA)、Soft Defect Localization(SDL),发现异常。单元减薄后,对异常位置进行电子-光学探测(EOP)和横截面检查。在FA中发现了金属间的高阻性导电。优化后的数据得到了良好的探头测试性能,提高了集成电路的质量。极低压试验可以筛选出正常的低压缺陷。超低电压直流扫描测试取代了传统的普通低压直流扫描测试,减少了探头测试时间。结果表明,极低压测试是保证芯片质量、提高缺陷覆盖率、筛选出薄弱集成电路、降低测试成本的良好测试方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Investigate for Very-Low-Voltage Test Implemented In Probe
Integrated circuit (IC) manufacturers perform production tests to detect defective part to guarantee the quality level of the product. Weak ICs contain flaws, defects that do not cause functional failures at some or all normal operating conditions but degrade the ICs performance, reduce noise margins, or draw excessive supply current. The current normal Low voltage test is not able to defect weak ICs or eliminate the early-life failures. The auto and military customers have very high quality requirement. Very-Low-voltage test can detect the defects (flaws) that cause early-life failures or intermittent failures. And the cost of Very-Low-Voltage test is very low. Very-Low-Voltage testing is a method where a test is performed at a supply voltage that is much lower than its nominal operating voltage. It can detect resistive shorts and delay flaws that are caused by degraded signals or diminished-drive gates. It can be implemented in die level, and no special equipment requirement of replacing the defect, which do not bring the additional cost. In this paper, the study aimed mainly at Very-Low-Voltage implemented in DC Scan test at probe level, and the core voltage value of DC scan test for different domains setup is discussed. JMP software is data analysis tool used in the study, including data comparison among DOM1, DOM2, DOM3 and ARM core. Optimized the core voltage, determining the best parameters to be used, and implemented it in probe program. Collected the real probe Very-Low-Voltage rejects and do Electric and Physical Failure Analysis(FA). For the failure unit, diagnostic, shmoo analysis between Level (VDD_SOC_CAP) and Period, Laser Assisted Device Alteration(LADA), and Soft Defect Localization(SDL) were performed on failure unit, and the anomaly was found. After the unit was thinned, Electron-Optical Probing(EOP) and cross section were performed on the anomaly location. The high resistive conduct among metal is found in FA. With the optimized data, the good probe test performance was get, and improved ICs quality. The Very-Low-Voltage test can screen out the normal low voltage rejects. The traditional normal low voltage DC Scan tests were replaced by Very-Low-Voltage DC Scan tests, which also reduce the probe test time. It is concluded that the Very-Low-Voltage test is good test method in probe to guarantee the die quality, improve the defect coverage, screen out the weak ICs, and reduce the test cost.
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