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RF Front End Module Architectures for 5G 5G射频前端模块架构
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI: 10.1109/BCICTS45179.2019.8972735
F. Balteanu
{"title":"RF Front End Module Architectures for 5G","authors":"F. Balteanu","doi":"10.1109/BCICTS45179.2019.8972735","DOIUrl":"https://doi.org/10.1109/BCICTS45179.2019.8972735","url":null,"abstract":"Worldwide adoption of 3G/4G smartphones for more than 5 billion of people has been one of the main driving engine behind semiconductor industry. 5G is expected to bring higher data capacity, low latency and new RF hardware enhancements which will open the market for new application where our smartphones will be a conduit. CMOS lower features nodes as FinFET 7nm/14nm CMOS allow the computational power and lower power consumption required for the use of digital signal processing and RF digital calibration which are essential for 4G/5G modem and application processor technology. The goal of having a single die for the entire 4G/5G functionality has faded away to a more realistic partitioning where many RF and analogue blocks are integrated with other components such as RF acoustic filters in multiple RF front-endmodules. This paper presents RF front end architectures which will be part of 5G smartphones together with circuit and measurement details.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116856421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A THz Pulse Radiator Based on PIN Diode Reverse Recovery 基于PIN二极管反向恢复的太赫兹脉冲辐射器
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI: 10.1109/BCICTS45179.2019.8972736
Sam Razavian, A. Babakhani
{"title":"A THz Pulse Radiator Based on PIN Diode Reverse Recovery","authors":"Sam Razavian, A. Babakhani","doi":"10.1109/BCICTS45179.2019.8972736","DOIUrl":"https://doi.org/10.1109/BCICTS45179.2019.8972736","url":null,"abstract":"This paper presents a fully integrated oscillator-less THz pulse radiator based on reverse recovery of a PIN diode implemented using 130-nm SiGe BiCMOS technology. The chip radiates a wideband frequency comb in the THz regime through an on-chip antenna. The spacing between the THz tones can be programmed up to 10.5 GHz by tuning the frequency of the input trigger. The spectrum of the radiated frequency comb is measured from 320 GHz to 1.1 THz with 5.5-GHz spacing between the tones. The Non-Linear Q-Switching Impedance (NLQSI) technique is used for tuning the frequency tones and increasing the stability of the output stage. At a distance of 4 cm from the pulse radiator, the measured SNRs (including the losses) with 1 Hz resolution bandwidth are 51, 40, and 21 dB at 0.6, 0.8, and 1 THz, respectively with a 10-dB line-width of less than 2 Hz. With a 5.5-GHz input trigger, the total power consumption of the chip is 45 mW, with 20 mW consumed by the driver stage.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125000361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
300-GHz 120-Gb/s Wireless Transceiver with High-Output-Power and High-Gain Power Amplifier Based on 80-nm InP-HEMT Technology 基于80nm InP-HEMT技术的300-GHz 120gb /s高输出功率高增益无线收发器
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI: 10.1109/BCICTS45179.2019.8972756
H. Hamada, T. Tsutsumi, G. Itami, H. Sugiyama, H. Matsuzaki, K. Okada, H. Nosaka
{"title":"300-GHz 120-Gb/s Wireless Transceiver with High-Output-Power and High-Gain Power Amplifier Based on 80-nm InP-HEMT Technology","authors":"H. Hamada, T. Tsutsumi, G. Itami, H. Sugiyama, H. Matsuzaki, K. Okada, H. Nosaka","doi":"10.1109/BCICTS45179.2019.8972756","DOIUrl":"https://doi.org/10.1109/BCICTS45179.2019.8972756","url":null,"abstract":"A 300-GHz wireless transceiver (TRx) with a record data rate of 120 Gb/s was developed using an InP-based high-electron-mobility-transistors (InP-HEMTs). The power amplifier (PA), which is the key component of our TRx, was designed and fabricated to have high output power and gain with a combination of two- and 4-finger HEMTs and a low-impedance inter-stage matching technique. The measured small signal gain of the PA module was larger than 15 dB from 274 to 303 GHz. The saturated output power and output power at 1-dB gain compression point were 12 and 6 dBm, respectively. Using this PA and a 300-GHz fundamental mixer, we constructed our 300-GHz TRx. Wireless data transmissions of the TRx with a link distance of 9.8 m were carried out. Data transmissions of 120 and 100.2 Gb/s were successfully demonstrated for 16QAM and 64QAM, respectively. To the best of our knowledge, these are the highest data rates achieved with an electronics-based TRx around 300 GHz.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125569801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Virtual-Source Modeling of N-polar GaN MISHEMTS n极GaN MISHEMTS的虚拟源建模
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI: 10.1109/BCICTS45179.2019.8972774
Rohit R. Karnaty, U. Mishra, J. Buckwalter, M. Guidry, P. Shrestha, B. Romanczyk, N. Hatui, Xun Zheng, C. Wurm, Haoran Li, S. Keller
{"title":"Virtual-Source Modeling of N-polar GaN MISHEMTS","authors":"Rohit R. Karnaty, U. Mishra, J. Buckwalter, M. Guidry, P. Shrestha, B. Romanczyk, N. Hatui, Xun Zheng, C. Wurm, Haoran Li, S. Keller","doi":"10.1109/BCICTS45179.2019.8972774","DOIUrl":"https://doi.org/10.1109/BCICTS45179.2019.8972774","url":null,"abstract":"Nitrogen-polar (N-polar) Gallium Nitride (GaN) deep-recess high-electron mobility transistors (HEMTs) have demonstrated exceptional power density (8 W/mm) and high efficiency at 30 and 94 GHz. Unlike the conventional Galliumpolar GaN which have typical Silicon Nitride passivation, the Npolar deep-recess structure has a GaN cap layer added in the access region of the transistor to enhance the conductivity while reducing the DC-to-RF dispersion. Previously, the MIT virtual source (VS) model has been proposed as a physics-based approach to modeling Ga-polar devices. This work investigates the application of the VS model to N-polar GaN HEMTs. We present a comparison of DC-IV between the developed model and a fabricated device to demonstrate good agreement.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115178845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Development of SiGeSn Technique towards Integrated Mid-Infrared Photonics Applications SiGeSn技术在中红外集成光子学中的应用进展
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI: 10.1109/BCICTS45179.2019.8972759
Shui-Qing Yu, Yiyin Zhou, Huong Tran, Baohua Li, S. Ghetmiri, A. Mosleh, M. Mortazavi, W. Du, G. Sun, R. Soref, J. Margetis, J. Tolle
{"title":"Development of SiGeSn Technique towards Integrated Mid-Infrared Photonics Applications","authors":"Shui-Qing Yu, Yiyin Zhou, Huong Tran, Baohua Li, S. Ghetmiri, A. Mosleh, M. Mortazavi, W. Du, G. Sun, R. Soref, J. Margetis, J. Tolle","doi":"10.1109/BCICTS45179.2019.8972759","DOIUrl":"https://doi.org/10.1109/BCICTS45179.2019.8972759","url":null,"abstract":"GeSn DHS and QW lasers and photoconductors have been investigated. For laser, the maximum operation temperature of 270 K and wavelength of 3.5 µm were achieved; for detector, spectral cut-off was measured at 3.6 µm.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117002572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Computationally Efficient Modelling Methodology for Field-Plates in GaN HEMTs 氮化镓hemt场极板的高效计算建模方法
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI: 10.1109/BCICTS45179.2019.8972734
Jason Hodges, S. Albahrani, S. Khandelwal
{"title":"A Computationally Efficient Modelling Methodology for Field-Plates in GaN HEMTs","authors":"Jason Hodges, S. Albahrani, S. Khandelwal","doi":"10.1109/BCICTS45179.2019.8972734","DOIUrl":"https://doi.org/10.1109/BCICTS45179.2019.8972734","url":null,"abstract":"Multiple field-plates (FP) are employed in typical GaN HEMTs for improving the device performance. In industry standard models, FP regions are modelled by adopting a full HEMT device model. As a result, a GaN HEMT device with two field plates requires the computation of equations which are the equivalent of three HEMT devices; one for the channel region, and two for the field-plate regions. This causes computational inefficiency. In this paper, we present a simplified field-plate modelling methodology which reduces the computational expense through means of approximations whilst maintaining an excellent degree of accuracy. Using insights from TCAD simulations, we develop simplifications for modelling the FP regions, improving the overall model speed. The developed methodology is validated against the TCAD data showing excellent accuracy and significant model speed improvement over the industry standard model.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117072608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 60 GS/s 8-b DAC with > 29.5dB SINAD up to Nyquist frequency in 7nm FinFET CMOS 60gs /s 8-b DAC， > 29.5dB SINAD，最高奈奎斯特频率，用于7nm FinFET CMOS
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI: 10.1109/BCICTS45179.2019.8972740
Y. Greshishchev, Tingjun Wen, Naim Ben-Hamida, J. Aguirre, S. Aouini, M. Besson, R. Gibbins, Y. Cho, Jerry Lam, D. McPherson, M. Parvizi
{"title":"A 60 GS/s 8-b DAC with > 29.5dB SINAD up to Nyquist frequency in 7nm FinFET CMOS","authors":"Y. Greshishchev, Tingjun Wen, Naim Ben-Hamida, J. Aguirre, S. Aouini, M. Besson, R. Gibbins, Y. Cho, Jerry Lam, D. McPherson, M. Parvizi","doi":"10.1109/BCICTS45179.2019.8972740","DOIUrl":"https://doi.org/10.1109/BCICTS45179.2019.8972740","url":null,"abstract":"CMOS FinFET is a leading technology choice for state-of-the-art DSP ASICs, where achieving a high signal to noise and distortion ratio (SINAD) in the transmitter DAC becomes one of the analog design challenges. This paper presents a 60 GS/s 8-b DAC in 7nm FinFET CMOS with SINAD close to 30 dB up to the Nyquist frequency.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121201222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High-Performance InGaAs-on-Silicon Technology Platform For Logic and RF Applications 用于逻辑和射频应用的高性能InGaAs-on-Silicon技术平台
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI: 10.1109/BCICTS45179.2019.8972722
C. Zota, C. Convertino, M. Sousa, D. Caimi, K. Moselund, L. Czornomaz
{"title":"High-Performance InGaAs-on-Silicon Technology Platform For Logic and RF Applications","authors":"C. Zota, C. Convertino, M. Sousa, D. Caimi, K. Moselund, L. Czornomaz","doi":"10.1109/BCICTS45179.2019.8972722","DOIUrl":"https://doi.org/10.1109/BCICTS45179.2019.8972722","url":null,"abstract":"An InGaAs-on-Si MOSFET technology platform using a CMOS-compatible fabrication flow is demonstrated. Several channel heterostructure designs are explored, with the use of thin InP barrier layers resulting in significant enhancement of mobility. MOSFETs with ft/fmax of ~350/350 GHz are demonstrated. Within the same technology platform, logic FinFET devices are also demonstrated, with record-high on-currents of 350 µA/µm. The use of S/D spacers to mitigate the parasitic bipolar effect is also explored, leading to significant reduction of off-state leakage currents. Finally, 3D sequential integration of InGaAs MOSFETs on SOI CMOS wafers is reported, showing no degradation of CMOS performance post top-level fabrication. The results indicate the strong potential for integrated InGaAs FETs towards high-performance logic and mixed-signal applications.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133383114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Welcome from BCICTS 2019 Co-Chairs 欢迎各位BCICTS 2019联合主席
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI: 10.1109/bcicts45179.2019.8972743
{"title":"Welcome from BCICTS 2019 Co-Chairs","authors":"","doi":"10.1109/bcicts45179.2019.8972743","DOIUrl":"https://doi.org/10.1109/bcicts45179.2019.8972743","url":null,"abstract":"","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132578818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Broadband Reflection-Type Phase Shifter Achieving Uniform Phase and Amplitude Response across 27 to 31 GHz 一种宽带反射型移相器，实现27至31 GHz的均匀相位和幅度响应
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2019-11-01 DOI: 10.1109/BCICTS45179.2019.8972730
Yuanrung Chang, B. Floyd
{"title":"A Broadband Reflection-Type Phase Shifter Achieving Uniform Phase and Amplitude Response across 27 to 31 GHz","authors":"Yuanrung Chang, B. Floyd","doi":"10.1109/BCICTS45179.2019.8972730","DOIUrl":"https://doi.org/10.1109/BCICTS45179.2019.8972730","url":null,"abstract":"This paper demonstrates a broadband reflection-type phase shifter (RTPS) for millimeter-wave phased-array applications. Implemented in 45-nm SOI CMOS, the proposed bidirectional RTPS provides a full 360 deg. phase-shift with a five-bit phase resolution. It incorporates an additional series inductor/varactor resonator to a Pi-based varactor/inductor/varactor network to broaden both the phase-shift range and bandwidth and to allow a single set of voltages to control the RTPS response over the full 27 to 31 GHz bandwidth (13.8% fractional bandwidth). A method is proposed to select these control voltages under an intended insertion-loss constraint to minimize the average root-mean squared (RMS) phase error across the entire band. Across the full band, the RTPS achieves an RMS phase error less than 3.8 deg, insertion loss of 8.5 to 10 dB, and RMS gain error less than 0.5 dB across the band.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127825080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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