用于逻辑和射频应用的高性能InGaAs-on-Silicon技术平台

C. Zota, C. Convertino, M. Sousa, D. Caimi, K. Moselund, L. Czornomaz
{"title":"用于逻辑和射频应用的高性能InGaAs-on-Silicon技术平台","authors":"C. Zota, C. Convertino, M. Sousa, D. Caimi, K. Moselund, L. Czornomaz","doi":"10.1109/BCICTS45179.2019.8972722","DOIUrl":null,"url":null,"abstract":"An InGaAs-on-Si MOSFET technology platform using a CMOS-compatible fabrication flow is demonstrated. Several channel heterostructure designs are explored, with the use of thin InP barrier layers resulting in significant enhancement of mobility. MOSFETs with ft/fmax of ~350/350 GHz are demonstrated. Within the same technology platform, logic FinFET devices are also demonstrated, with record-high on-currents of 350 µA/µm. The use of S/D spacers to mitigate the parasitic bipolar effect is also explored, leading to significant reduction of off-state leakage currents. Finally, 3D sequential integration of InGaAs MOSFETs on SOI CMOS wafers is reported, showing no degradation of CMOS performance post top-level fabrication. The results indicate the strong potential for integrated InGaAs FETs towards high-performance logic and mixed-signal applications.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High-Performance InGaAs-on-Silicon Technology Platform For Logic and RF Applications\",\"authors\":\"C. Zota, C. Convertino, M. Sousa, D. Caimi, K. Moselund, L. Czornomaz\",\"doi\":\"10.1109/BCICTS45179.2019.8972722\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An InGaAs-on-Si MOSFET technology platform using a CMOS-compatible fabrication flow is demonstrated. Several channel heterostructure designs are explored, with the use of thin InP barrier layers resulting in significant enhancement of mobility. MOSFETs with ft/fmax of ~350/350 GHz are demonstrated. Within the same technology platform, logic FinFET devices are also demonstrated, with record-high on-currents of 350 µA/µm. The use of S/D spacers to mitigate the parasitic bipolar effect is also explored, leading to significant reduction of off-state leakage currents. Finally, 3D sequential integration of InGaAs MOSFETs on SOI CMOS wafers is reported, showing no degradation of CMOS performance post top-level fabrication. The results indicate the strong potential for integrated InGaAs FETs towards high-performance logic and mixed-signal applications.\",\"PeriodicalId\":243314,\"journal\":{\"name\":\"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)\",\"volume\":\"77 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BCICTS45179.2019.8972722\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS45179.2019.8972722","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

演示了采用cmos兼容制造流程的InGaAs-on-Si MOSFET技术平台。探索了几种通道异质结构设计,使用薄的InP势垒层可以显著提高迁移率。演示了ft/fmax为~350/350 GHz的mosfet。在相同的技术平台上,逻辑FinFET器件也被展示,具有350µA/µm的创纪录高导通电流。研究人员还探索了使用S/D间隔器来减轻寄生双极效应,从而显著降低了非状态泄漏电流。最后,报道了InGaAs mosfet在SOI CMOS晶圆上的3D顺序集成,显示顶层制造后CMOS性能没有下降。结果表明,集成InGaAs fet在高性能逻辑和混合信号应用方面具有强大的潜力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High-Performance InGaAs-on-Silicon Technology Platform For Logic and RF Applications
An InGaAs-on-Si MOSFET technology platform using a CMOS-compatible fabrication flow is demonstrated. Several channel heterostructure designs are explored, with the use of thin InP barrier layers resulting in significant enhancement of mobility. MOSFETs with ft/fmax of ~350/350 GHz are demonstrated. Within the same technology platform, logic FinFET devices are also demonstrated, with record-high on-currents of 350 µA/µm. The use of S/D spacers to mitigate the parasitic bipolar effect is also explored, leading to significant reduction of off-state leakage currents. Finally, 3D sequential integration of InGaAs MOSFETs on SOI CMOS wafers is reported, showing no degradation of CMOS performance post top-level fabrication. The results indicate the strong potential for integrated InGaAs FETs towards high-performance logic and mixed-signal applications.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信