C. Zota, C. Convertino, M. Sousa, D. Caimi, K. Moselund, L. Czornomaz
{"title":"用于逻辑和射频应用的高性能InGaAs-on-Silicon技术平台","authors":"C. Zota, C. Convertino, M. Sousa, D. Caimi, K. Moselund, L. Czornomaz","doi":"10.1109/BCICTS45179.2019.8972722","DOIUrl":null,"url":null,"abstract":"An InGaAs-on-Si MOSFET technology platform using a CMOS-compatible fabrication flow is demonstrated. Several channel heterostructure designs are explored, with the use of thin InP barrier layers resulting in significant enhancement of mobility. MOSFETs with ft/fmax of ~350/350 GHz are demonstrated. Within the same technology platform, logic FinFET devices are also demonstrated, with record-high on-currents of 350 µA/µm. The use of S/D spacers to mitigate the parasitic bipolar effect is also explored, leading to significant reduction of off-state leakage currents. Finally, 3D sequential integration of InGaAs MOSFETs on SOI CMOS wafers is reported, showing no degradation of CMOS performance post top-level fabrication. The results indicate the strong potential for integrated InGaAs FETs towards high-performance logic and mixed-signal applications.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High-Performance InGaAs-on-Silicon Technology Platform For Logic and RF Applications\",\"authors\":\"C. Zota, C. Convertino, M. Sousa, D. Caimi, K. Moselund, L. Czornomaz\",\"doi\":\"10.1109/BCICTS45179.2019.8972722\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An InGaAs-on-Si MOSFET technology platform using a CMOS-compatible fabrication flow is demonstrated. Several channel heterostructure designs are explored, with the use of thin InP barrier layers resulting in significant enhancement of mobility. MOSFETs with ft/fmax of ~350/350 GHz are demonstrated. Within the same technology platform, logic FinFET devices are also demonstrated, with record-high on-currents of 350 µA/µm. The use of S/D spacers to mitigate the parasitic bipolar effect is also explored, leading to significant reduction of off-state leakage currents. Finally, 3D sequential integration of InGaAs MOSFETs on SOI CMOS wafers is reported, showing no degradation of CMOS performance post top-level fabrication. The results indicate the strong potential for integrated InGaAs FETs towards high-performance logic and mixed-signal applications.\",\"PeriodicalId\":243314,\"journal\":{\"name\":\"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)\",\"volume\":\"77 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BCICTS45179.2019.8972722\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS45179.2019.8972722","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-Performance InGaAs-on-Silicon Technology Platform For Logic and RF Applications
An InGaAs-on-Si MOSFET technology platform using a CMOS-compatible fabrication flow is demonstrated. Several channel heterostructure designs are explored, with the use of thin InP barrier layers resulting in significant enhancement of mobility. MOSFETs with ft/fmax of ~350/350 GHz are demonstrated. Within the same technology platform, logic FinFET devices are also demonstrated, with record-high on-currents of 350 µA/µm. The use of S/D spacers to mitigate the parasitic bipolar effect is also explored, leading to significant reduction of off-state leakage currents. Finally, 3D sequential integration of InGaAs MOSFETs on SOI CMOS wafers is reported, showing no degradation of CMOS performance post top-level fabrication. The results indicate the strong potential for integrated InGaAs FETs towards high-performance logic and mixed-signal applications.