{"title":"Si3N4 extrinsic defects and capacitor reliability","authors":"J. Scarpulla, E. E. King, J. V. Osborn","doi":"10.1109/IRPS.2011.5784456","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784456","url":null,"abstract":"The capacitors implemented in RF/microwave MMICs seem to dominate the reliability in many cases, rather than the active devices (pHEMTs or HBTs) themselves. We have examined MIMCAP extrinsic defect density by extracting it from published data available in the open literature. The methodology for extracting defect densities from probability plots of times to breakdown or of ramped breakdown voltages is shown. We have noted that the extrinsic densities are quite varied across the dozen sets of data compiled. We also contributed data using Hg-dot-formed capacitors. Using this industry-wide data we provide some design charts for the sizing of capacitors in MMICs based upon their extrinsic reliability.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129616438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"WCDM2 — Wafer-level charged device model testing with high repeatability","authors":"N. Jack, T. Maloney, B. Chou, E. Rosenbaum","doi":"10.1109/IRPS.2011.5784509","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784509","url":null,"abstract":"CDM-like unipolar pulses are generated at the wafer level with excellent repeatability and linearity. Pulse width and rise time resemble that of FICDM testers. In-situ pre- and post-stress curve tracing reveals the current failure threshold for the device under test.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127675466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lu-An Chen, Chang-Tzu Wang, T. Lai, Tien-Hao Tang, K. Su
{"title":"The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications","authors":"Lu-An Chen, Chang-Tzu Wang, T. Lai, Tien-Hao Tang, K. Su","doi":"10.1109/IRPS.2011.5784564","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784564","url":null,"abstract":"In this work, the MPSCR structure have been verified in a 0.35-um 40-V CDMOS technology. The MPSCR structure with high ESD robustness has been clearly investigated by TLP instrument and TCAD simulator. By the simulation results, the modified P+ electrode layout of cathode side can enhance the turn-on efficiency of embedded SCR path, and avoid the current crowding effect on the surface of device. The proposed device only need to sweep N+ and P+ regions in drain side, and do not need to increase the additional mask layer. For area reduction, the MPSCR device does not need to increase the layout area and it can sustain up to 7.2kV for HBM and 360V for MM under device width of 300µm. Besides, the proposed MPSCR device has a low trigger voltage (Vt1=54-V) and a high second breakdown current (It2=10-A), which can be extensively applied for ESD protection design of PMIC applications.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128545808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Tega, H. Miki, Z. Ren, C. D'Emic, Yu Zhu, D. Frank, M. Guillorn, Dae-gyu Park, W. Haensch, K. Torii
{"title":"Impact of HK / MG stacks and future device scaling on RTN","authors":"N. Tega, H. Miki, Z. Ren, C. D'Emic, Yu Zhu, D. Frank, M. Guillorn, Dae-gyu Park, W. Haensch, K. Torii","doi":"10.1109/IRPS.2011.5784546","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784546","url":null,"abstract":"This work demonstrates the close relationship between device scaling and the threshold voltage variation (ΔVth) of random telegraph noise (RTN) in high-κ and metal gate (HK / MG) stacks. Statistical analysis clarifies that high temperature forming gas annealing can suppress the RTN ΔVth. And properly annealed HK FETs have smaller RTN ΔVth than SiON FETs, due mostly to fewer traps and partly to thinner inversion thickness in HK / MG stacks. Consequently, the influence of RTN on HK / MG gate stacks is less than that of random dopant fluctuation in the 22 nm generation. However, RTN may pose a difficult challenge for the 15 nm generation. In addition to the scaling dependence, we also find that characterizing hysteretic RTN behaviors due to RTN dependence on bias is essential to determine whether the observed RTN has an impact on SRAM operation or not.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115903252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Roy, E. Zhang, D. Fleetwood, peixiong zhao, Y. Puzyrev, S. Pantelides
{"title":"Reliability-limiting defects in AlGaN/GaN HEMTs","authors":"T. Roy, E. Zhang, D. Fleetwood, peixiong zhao, Y. Puzyrev, S. Pantelides","doi":"10.1109/IRPS.2011.5784512","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784512","url":null,"abstract":"Low-frequency noise measurements and density functional theory calculations are combined to show that N-anti-site and C impurity defects can lead to changes in the low frequency noise of GaN/AlGaN HEMTs fabricated with three typical process conditions. Implications for device reliability are discussed.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114403469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W.H. Liu, K. Pey, N. Raghavan, X. Wu, M. Bosman, T. Kauerauf
{"title":"Random telegraph noise reduction in metal gate high-κ stacks by bipolar switching and the performance boosting technique","authors":"W.H. Liu, K. Pey, N. Raghavan, X. Wu, M. Bosman, T. Kauerauf","doi":"10.1109/IRPS.2011.5784474","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784474","url":null,"abstract":"In high-κ (HfSiON and HfLaO) metal gate stacks, the traps leading to gate current Ig random telegraph noise (RTN) are found to be effectively passivated by bipolar switching from negative gate bias, where RTN and threshold voltage variation (ΔVT) are reduced significantly or even disappear. The reduction of RTN, ΔVT and Ig in degraded gate dielectrics is modeled by oxygen ion drift from the oxygen gettering metal gate electrode to re-passivate the traps upon negative gate bias. A performance boosting technique for transistors during operation is proposed. In this technique, the gate is swept by a small negative voltage to induce a bipolar switching and thus boost up performance after long duration of operation.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116069761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
U. Kindereit, Oana-Mihaela Mutihac, C. Boit, B. Tillack
{"title":"Spectral resolution of photon emission from SiGe:C heterojunction bipolar transistors (HBTs)","authors":"U. Kindereit, Oana-Mihaela Mutihac, C. Boit, B. Tillack","doi":"10.1109/IRPS.2011.5784527","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784527","url":null,"abstract":"This publication presents photon emission measurements of SiGe:C-HBTs acquired with Si-CCD and InGaAs detector, proving the InGaAs-camera capability for this application. The emission characteristic helps distinguish operating modes like saturation, active or avalanche. Spectral response shows a local maximum at 1300 nm, representing the decreased bandgap due to additional germanium.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116293141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Vandelli, A. Padovani, L. Larcher, G. Bersuker, J. Yum, P. Pavan
{"title":"A physics-based model of the dielectric breakdown in HfO2 for statistical reliability prediction","authors":"L. Vandelli, A. Padovani, L. Larcher, G. Bersuker, J. Yum, P. Pavan","doi":"10.1109/IRPS.2011.5784582","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784582","url":null,"abstract":"We present a quantitative physical model describing the current evolution due to the formation of a conductive filament responsible for the HfO2 dielectric breakdown. By linking the microscopic properties of the stress-generated electrical defects to the local power dissipation and to the corresponding temperature increase along the conductive path the model reproduces the rapid current increase observed during the breakdown. The model successfully simulates the experimental time-dependent dielectric breakdown distributions measured in HfO2 MIM capacitors under constant voltage stress, thus providing a statistical reliability prediction capability, which can be extended to other high-k materials, multilayer stacks, resistive memories based on transition metal oxides, etc.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114910449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Hsu, Wen-Chin Lin, T. Tsai, Climbing Huang, J. Wu
{"title":"A model for post-CMP cleaning effect on TDDB","authors":"C. Hsu, Wen-Chin Lin, T. Tsai, Climbing Huang, J. Wu","doi":"10.1109/IRPS.2011.5784554","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784554","url":null,"abstract":"For 45 nm and beyond, direct polished porous type ultra low-K film (ULK) is integrated in Cu interconnects. Post-cleaning of Cu CMP effect on Time dependent dielectric breakdown (TDDB) was investigated. Cu ions remaining on dielectrics and Cu roughness are found as two dominate factors at different clean time region. High Cu roughness induced capping layer seam results in the degradation of TDDB. A statistical model, said weak element model, was proposed to illustrate the correlation of Cu roughness on TDDB as well.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127315765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Malandruccolo, M. Ciappa, W. Fichtner, H. Rothleitner
{"title":"In situ screening techniques for defective oxides in devices for automotive applications","authors":"V. Malandruccolo, M. Ciappa, W. Fichtner, H. Rothleitner","doi":"10.1109/IRPS.2011.5784447","DOIUrl":"https://doi.org/10.1109/IRPS.2011.5784447","url":null,"abstract":"Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents novel built-in circuitries to screen out oxide defects in integrated circuits for the most important building blocks used in automotive applications. The proposed techniques are based on an embedded circuitry that includes control logic, high voltage generation, and leakage current monitoring. The concept and advantages of the proposed screening procedure are described in very detail and demonstrated experimentally in conjunction with the integration of test-chips.","PeriodicalId":242672,"journal":{"name":"2011 International Reliability Physics Symposium","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127551280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}