2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference最新文献

{"title":"Effect of silicon nitride deposition parameters on TDDB performance of SiNx-MIM capacitors","authors":"Xu Feng, N. H. Seng, Raymond Tan Kok Hong","doi":"10.1109/IEMT.2016.7761973","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761973","url":null,"abstract":"Silicon nitride (SiNx) is commonly used as the dielectric or insulator material for metal-insulator-metal (MIM) capacitors. The deposition of SiNx can be performed using plasma-enhanced chemical vapor deposition (PECVD) method with different deposition parameters by changing individually the SiH4 flow rates, NH3 flow rates, RF power, substrate temperature, etc. Time-dependent dielectric breakdown (TDDB) is the most important reliability test item to check the intrinsic performance of the MIM capacitor dielectrics. In this study, the effect of several SiNx deposition parameters on the dielectric TDDB performance of SiNx MIM capacitors has been studied: silane (SiH4) gas flow rate, RF power and ammonia (NH3) gas flow rate. The constant voltage TDDB lifetime performances for different conditions were compared and discussed for MIM capacitor optimization and the mechanism behind the effect was discussed.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122695783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High voltage isolation silicon node wafer saw","authors":"Wan Md Misuari Bin Wan Suleiman, Nageswararau Krishnan","doi":"10.1109/IEMT.2016.7761939","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761939","url":null,"abstract":"Texas Instruments' high voltage isolation semiconductor devices enable safe transmission of data and power between high voltage and low voltage circuits in modern electrical systems. The silicon technology for isolation contains higher metallization content in the wafer saw street and therefore, requires the assembly dicing process window to be well characterized to enable robust manufacturing and quality. This paper provides an overview of mechanisms that induce top side and flipside silicon chipping, analyzes the impact of metal density in wafer saw street on chipping severity, and discusses the attributes in mechanical saw process that can be characterized to prevent chipping defects in high volume manufacturing.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128963419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Crack die elimination by comprehensive optimization throughout all assembly process steps","authors":"W. L. Chin, C. E. Tan, Norsholiha Mohd Shauffi","doi":"10.1109/IEMT.2016.7761943","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761943","url":null,"abstract":"Over years, the crack die defect was proven cannot be screened effectively through Final Test, therefore it has high risk reaching the end applications. This issue can affect many devices, including some miniature devices such as Small Outline Transistors, SOTXXX Eutectic. In order to eliminate the die crack defect, entire assembly process required optimization; including Saw, Die Attach, Wire Bond, Mold, Plating, Trim/Form and Final Test. Each process step has its own risks and therefore full analysis was conducted on all the possible opportunities. At wafer sawing process, several sawing methods were evaluated, including single cut, step cut, 3 channels cutting, cutting directions and selection of various blade types. With the optimum sawing process, die chipping was minimized to lowest level (only few microns), that resulting to minimum die cracking risk. With that performance, further risk investigation was carried on to understand the stress amount inside the package. There were 2 significant stress factors, die location on flag and trim/form impact to the leads. In order to minimize the effect of the stress, die was attached to the location with the least amount of stress. As for trim/form, this involved new design leadframe fabricated and experimented in production. The leadframe design optimization was completed after compliance to the reasonable stress level, as calculated in the trim/form stress analysis. When new leadframe was subjected to actual trim/form process, actual performance was verified by reliability testing. With the optimum assembly configurations, further safety action was depended to the Final Test capability. There were 2 additional test parameters added to increase effectiveness of screening potential die crack rejects. With the total compilation of all the optimum assembly and test configurations, actual performance monitoring showed total elimination of die crack occurrence. This project becomes good benchmark of any die crack reduction or elimination project.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121064485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of polyimide coated chip and mold compound adhesion","authors":"M. T. Asmah","doi":"10.1109/IEMT.2016.7761977","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761977","url":null,"abstract":"This study investigates the adhesion strength between polyi-mide coated chip and epoxy mold compound (EMC). Polyi-mide is an important material to reduce chip stress and protect the mobility ions from EMC to the chip circuitry that can lead to an electrical failure. However, there was a delamination issue between encapsulation material and polyimide during reliability test. Two samples were prepared named as EMC A (sample without adhesion promoter) and EMC B (sample with adhesion promoter). Prior to curing process, wafers were coated with 7±1 μm thickness of polyimide using spin coating process. Then, samples were cured at 175 °C for 5 hours in oven after molding process. Samples were then soaked in the Autoclave test chamber (ACLV) at 121°C with 100% relative humidity (RH) for 0.5 hour, 1 hour, 1.5 hours and 2 hours to test the sample reliability. Adhesion strength was measured at room temperature and 260 °C. In addition, water absorption with varies moisture sensitivity level (MSL) was carried out. The MSL test was set for three level which were 85 °C / 85% RH, 85 °C / 60% RH and 30 °C / 60% RH for level 1, 2 and 3, respectively. There was a significant different on moisture absorption but less significant in delamination response. Based on the strength test, EMC B showed a gap between polyimide and mold compound after 0.5 hour of ACLV test while no gap was observed for EMC A even after 2 hours of ACLV test. It could be concluded that EMC that formulated with adhesion promoter provided significant factor to the delamination issue compared with EMC without adhesion promoter.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134066252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An alternative format for plastic packaging — Wafer/panel level encapsulation: Its challenges and solutions","authors":"Kuah Teng Hock, E. Kuah, Wu Kai, H. Yuan, C. W. Ling, Dam Duc Tai, Ho Shu Chuen","doi":"10.1109/IEMT.2016.7761907","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761907","url":null,"abstract":"This work will discourse on the challenges and solutions that a packaging and/or equipment engineer will face during the molding process of 5S (five-sided) and/or 6S (six-sided) packages at a wafer and/or panel level. This form of packaging is known as large format packaging (LFP). Technical solutions and in particular encapsulation assembly are discussed from the viewpoint of drivers of LFP, CLAP design, encapsulation equipment/tool design, encapsulant and moldability. Based on this work, LFP as a packaging solution is a viable option provided that package co-planarity, optimal encapsulant design, and optimized molding process are enforced. The keys are optimization of equipment, tool and molding process control.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"474 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132341601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cost savings through innovative and LEAN engineering approach for wireless modules","authors":"Foo Chong Seng, Tan Jui Ang","doi":"10.1109/IEMT.2016.7761988","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761988","url":null,"abstract":"One of the wireless module required additional Thermal Interface Material (TIM) and Electro Magnetic Interference (EMI) absorber in order for the product to function per requirement. In order to place these two items onto the module, the one piece shield will need to be replaced by 2 pieces shield - shield fence & shield lid. All these additional BOM items will need to be assembled and inspected manually by operators. This resulted in significant increase of cycle time needed for the assembly and inspection process which causes ODM to increase their Manufacturing Value Adder (MVA). Total BOM cost also increased significantly for those three additional items. As the results, Instead of achieving generation product cost reduction, the cost for that generation of wireless products actually went up. This presentation will illustrate the key challenges faced and the approach that we have taken mainly through Process Automation, LEAN waste elimination and Process Shift Left to supplier. These innovative and holistic three phases approach enable huge cycle time reduction (91%) for the additional processes in ODM and achieve significant cost savings across the life cycle of the product.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115136592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced low-k die singulation defect inspection and pre-emptive singulation defect detection","authors":"W. Fitzgerald, Rajiv Roy","doi":"10.1109/IEMT.2016.7761970","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761970","url":null,"abstract":"Advanced packaging has a challenge on its hands in dealing with reliability issues caused during singulation. Specifically, in the case of Wafer Level Chip Scale packaging (WLCSP) where the sawn die edge is the package edge and is exposed. WLCSP manufactured on the newer nodes are based on Ultra-low K dielectric material. This material is inherently porous and mechanically fragile. During the singulation step, there is a likelihood of creating chipping and delamination. Rudolph have developed a comprehensive approach to detecting defects generated at the laser grooving and saw process steps. There are two recommended approaches. The first approach is an inspection approach that is focused on detecting the defects after it has occurred. The second, a more sophisticated approach is to attempt to pre-empt occurrence of defects. In the first approach-die seal ring inspection, algorithms have been developed around the die seal ring to ensure the die integrity. These algorithms not only include the capability to detect the defect but also measure the defect size, defect position and frequency of defects. All of this is done while minimizing false defects that are typically found due to street and reticle artifacts that are often falsely detected as chipping. This enables customers to perform advanced disposition to ensure the optimal balance between shipping good die and preventing the shipment of potential reliability fails. The second approach - Kerf metrology and Saw control comprises of Fault detection and classification (FDC) to record equipment data during the singulation processes and inspection equipment to detect surface defects such as chips, delamination and cracks. The combination of FDC to monitor equipment performance and the ability to correlate Metrology/Inspection performance data enables customers to not only detect defects but preemptively eliminate them. Poorly singulated dies can now be analyzed all the way back to the process equipment signals. Once these signals are identified they can be monitored to prevent or alert operators of possible excursions. These analytics will help customers define and ramp robust processes, justify consumable costs and ultimately lead to a better understanding of this difficult and challenging process. Finally, specific YMS capabilities exist to align and analyze the collected equipment and process data.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125138009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of etch rate against temperature, main hydrogen flow, power and top/vent for epitaxy cleaning recipe","authors":"W. Moy, K. Cheong","doi":"10.1109/IEMT.2016.7761952","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761952","url":null,"abstract":"For a standard silicon-epitaxy cleaning recipe, there are eight main steps; namely purge, ramp, bake, etch clean 1, etch clean 2, Trichlorosilane (TCS) purge, TCS coat and cooling steps. Cleaning is critical to clean the process chamber after epitaxy deposition is completed. Historically, acid hydrochloric etch is incorporated with hydrogen to clean and prepare the process chamber to ensure that a good quality of epitaxial growth can be achieved in the next process cycle. However, recipe of cleaning may impact throughput of the process with temperature higher than 1150°C at etch step. By varying the temperature, it may affect the time of ramping to achieve a set temperature as well as the time of stabilization at the set temperature. An attempt has been made to study the impact of etch rate against four important process parameters; namely temperature, main hydrogen flow, power and top/vent setting during cleaning process using a fractional factorial design - a two levels, four factor designs with sixteen unique treatment combinations are employed to determine the significant factors in the production of an optimum etch rate with minimum impact on generating defects (slip and particles) to the epitaxial layer. Etch rate, slip and particles are selected as the response for assessing the most significant factor that may affect quality of etching and cleaning of the chamber. The experimental variables are evaluated using regression model to estimate the relationships and predict the optimized parameters for a cleaning recipe after epitaxy process.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121566740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced interconnects through filled metal structures","authors":"Sameer Shekhar, A. Jain, C. Kuan","doi":"10.1109/IEMT.2016.7761944","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761944","url":null,"abstract":"This paper analyses use of solid metal fill between BGA balls or LGA pins of packages, and between die bumps. The basic principle is to benefit from higher metal-density per unit volume of the substrate in the current path to deliver enhanced electrical, thermal and mechanical performance. Paper conceptualizes different structures and simulated data is presented to show case benefits. Results show power delivery impedance peak reduction by 10 % in the 100 kHz-10 MHz range. In addition, package inductor benefit of 40 % lower DC resistance is reported.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128958532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical, microstructural, and surface roughness study of thermally oxidized metallic Sm thin film on Si substrate","authors":"K. H. Goh, A. Haseeb, Y. H. Wong","doi":"10.1109/IEMT.2016.7761971","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761971","url":null,"abstract":"Electrical, microstructural, and surface roughness of 150 nm sputtered pure samarium metal film on silicon substrates which thermal oxidized in oxygen ambient at various temperatures (600-900 °C) for 15 min have been investigated quantitatively. Effects of oxidation temperatures on the C-V characteristics, surface morphology, and surface roughness of Sm₂O₃ thin films were reported. The smooth and uniform of Sm₂O₃ thin films were revealed by scanning electron microscope and atomic force microscopy analysis. The sample oxidized at 700 °C demonstrated the smallest AV_PB value, lowest STD value (5.56 × 10¹² cm^-2) and D_it values (~10¹⁴ eV^-1 cm^-2).","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124659647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}