2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference最新文献

{"title":"Simulation and experimental study of Cu wedge bond reliability","authors":"Tao Xu, Jin Li, Jason Fu, C. Luechinger","doi":"10.1109/IEMT.2016.7761966","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761966","url":null,"abstract":"Copper (Cu) wire has many advantages and is replacing Aluminum (Al) wire in high performance power electronics. A power cycling test system was developed and cycling tests were performed to compare reliability of Al wire and Cu wire and to investigate how a wire surface defect and the bond process affect the reliability. A finite element analysis (FEA) model was created and simulations were run to analyze failure mechanisms of test samples. The results show Cu wire can carry more current, works at higher temperature, and has much better reliability. For both Al and Cu wires, stronger bonds have higher reliability and are less sensitive to wire surface defects. The defects affect bond reliability especially for lightly bonded wires. A wedge imprint at a bond from special wedge design does not affect the bond reliability even it appears similar to a surface defect.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134535571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The low Dk/Df polyimide adhesives for low transmission loss substrate","authors":"Takashi Tasaki, Atsushi Shiotani, Takashi Yamaguchi, Keisuke Sugimoto","doi":"10.1109/IEMT.2016.7761910","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761910","url":null,"abstract":"The advance of wireless communications and broadband technologies is dramatically progressing with the remarkable growth of the market of information technology equipments such as mobile phones and tablets. In order to meet ever-enlargement of transmitting data, transmission frequency in circuits tends to become high and the integrity of a high-frequency signal can be damaged by transmission loss. In high frequency circuits, two kinds of factors decide transmission loss. One is conductor (circuits) loss; the other is dielectric (insulating materials) loss. The former relates to skin effect of circuits. Skin effect is a tendency for an alternating current to flow mainly near surface of conductors. The general improving measure of conductor loss is smoothing a surface of circuits. However, smoothing a surface of circuits tends to weaken the adhesion between copper circuits and insulating materials. Accordingly, it is difficult for copper circuits to fulfill both smooth surface and good adhesion to insulating materials. Dielectric loss depends on current frequency and dielectric constant (Dk) and dielectric tangent (Df) of dielectric materials insulating conductive materials. Consequently, as current frequency become high, dielectric loss tend to increase, and the general improving measure of this loss is using low Dk and low Df materials. Hence Low Dk and Df materials with good adhesivity to smooth surface of copper are required for high frequency PCBs. We recently developed the novel solvent-soluble polyimides. Moreover, by using these materials, we got the low Dk, low Df adhesives with high heat resistance and good adhesivitiy to smooth copper such as rolled copper foils. In this presentation, we will report on properties of our polyimides and their adhesives and the trans mission loss evaluation of the substrate using the adhesive of these polyimides.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129837091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of MWCNT-based strain sensor using flexible substrate","authors":"K. Yumoto, Ken Suzuki, H. Miura","doi":"10.1109/IEMT.2016.7761980","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761980","url":null,"abstract":"Highly sensitive two-dimensional strain sensor, which consists of area-arrayed fine bundles of multi-walled carbon nanotubes (MWCNTs), has been developed by applying MEMS technology. Area-arrayed MWCNT bundles were grown on a substrate by CVD technique. When a compressive load was applied to the bundle, the electrical resistance of the bundle increased monotonically due to the change of the electronic band structure of the deformed CNT. By measuring the change of the resistance of each bundle, the two-dimensional distribution of the applied pressure was detected precisely. In the previous study, it was found that MWCNT bundle deformed repeatedly in the strain range up to 60%. Thus, in this study, the deformation behaviour of the MWCNT bundle on a flexible substrate, which is effective for rough surface, was observed. It was confirmed that the MWCNT bundle coated by PDMS showed elastic deformation under the application of axial compressive load of 60%, and the allowable maximum load was 3 mN.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123953507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bondability and reliability of Ag Alloy wire (92 and 95% Ag Alloy) on thin aluminum bonding pad","authors":"Jose Palagud, S. -. Wang","doi":"10.1109/IEMT.2016.7761948","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761948","url":null,"abstract":"There are several types of Ag Alloy wires being introduced for discrete IC manufacturing, a low (92%) and high purity level (95%) Ag Alloy wires are the most common one. The IC industries have been shifting to this type of wires due mainly to its lower cost and softer property as compared to gold and copper wire. Copper wire even with the improvements done such as alloying the material with palladium for improved reliability has limitations of usage for very thin top metallizations. At most 60-70% conversions have only been implemented to the usage of copper wire because of this main obstacle for BOAC (Bond Over Active Circuit) and devices with thin top metallization of at least 2um only are difficult to convert to copper wirebonding. Due to its relative hardness, higher parameter settings are required to make IMC (Intermetallic), and thin bonding pad metallization of AlSi or AlCu cannot withstand the compressive effect of this wire. This is specially observed for BSOB (Bond Stitch on Ball) wirebonding, where aside from the ball bonding, a stitch bond is placed on top of this ball bond. The impact coming from this additional bonding is adding severe compressive effect, for copper wires (usually Pd coated copper wire is use for BSOB) require high bond parameter to create an alloy effect or interconnection of hard copper ball and the bonding pad.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129214847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-destructive electrical test detection on copper wire micro-crack weld defect in semiconductor device","authors":"Robin Y. P. Ong, K. Cheong","doi":"10.1109/IEMT.2016.7761967","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761967","url":null,"abstract":"Structural integrity of wire bonding interconnection is having a significant impact on the quality of microelectronic devices. Conventional electrical test methodology is unable to detect 10 to 20 μm of cracks that exists in wire bond stitch weld (wedge bond) in semiconductor device. This type of crack is termed as micro-crack and it becomes prominent in Power MOSFET Molded Leadless Package. If the imperfect bonded electronic package does not screen out, it may create a potential interconnection failure during product lifetime. Typical industrial based testing method was unable to identify and isolate the failure packages. Therefore, this was the aim of this research to investigate another methodology [Time Domain Reflectometry (TDR)] for this purpose. In order to complement with the TDR results, other non-destructive [3D X-ray Computed Tomography (CT) inspection] and destructive [Scanning Electron Microscope (SEM)] test techniques were used. Novelty of this work is the non-destructive electrical test methodology that able to detect micro-crack defect at wedge bond in a Power MOSFET gate wire. This test methodology offers the short test time and provides high accuracy and efficiency test result. TDR has overcome the conventional test limitation and achieved a novel approach through the defined detection resolution for micro-crack weld.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127914224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solder joint reliability enhancement through surface mounting solder joint reflow optimization in enterprise grade solid state drives (SSDs)","authors":"Mohammad Zainudeen Moideen, C.L. Gan","doi":"10.1109/IEMT.2016.7761934","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761934","url":null,"abstract":"In high reliability Surface Mount Technology (SMT) assembly applications, the ability to inspect the solder joints visually has been standard and has been key factors in providing confidence in solder joint reliability. Inspection techniques such as X-ray can be used to detect gross manufacturing defects such as solder bridging, but are not suitable for detection of other defects such as cracks. Temperature cycling test (TCT) is a standard solder joint reliability assessment method in semiconductor reliability for ball grid array (BGA) packaging. SMT reflow process and CTE (coefficient of thermal expansion) between solder materials, PCB and BGA package have high influence in solder joint reliability. A careful experimental investigation was undertaken to evaluate the reliability of solder joints of SAC BGA components formed using Sn-2Ag-Cu-Ni solder paste. This evaluation specifically looked at the impact of time above liquidus, peak temperature and thermal interface material (TIM) on solder joint reliability. Four types of samples prepared with the peak temperature of 2500C and no TIM, 2500C with TIM, time above liquidus (TAL) 90 seconds and no TIM and TAL 90 seconds with TIM. A total of 60 drives were assembled and subjected to accelerated thermal cycling (ATC) test in the temperature range of 00C to 1000C for a maximum of 2000 cycles with reference to JESD22-A104 standard. Based on the results from the deisgn of experiment (DOE), TAL 90s profile have demonstrated better TCT reliability margin compared to peak temperature of 2500C.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124480776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Steps to prevent quality and reliability issues resulted from design optimization for productivity improvement","authors":"Rozazmi Bin Md Derus, Muhammad Syafiq Bin Roslan, Mohd Syafiq Bin Zainal, Hng May Ting, L. B. Huat","doi":"10.1109/IEMT.2016.7761968","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761968","url":null,"abstract":"Productivity improvement in manufacturing is always the key focus to strengthen an enterprise cost position to stay ahead of competition. In semiconductor manufacturing, improve the cost position through faster machine speed, reduce man to machine ratio, utilization of material efficiently, increase the through put per fix process cycle, and etc. are the common practices. In this paper, cost improvement is achieved through maximizing the number of packages per fix dimension of leadFrame (LF) and with minimum investment. The unit density per area of the LF has increased by 60% mainly through the introduction of through-gate design and increased number of rows per LF by 30%. However, the introduction of these measures have also increased the complexity of all the processes to manufacture the SSO8 package. The main focus of this study is on molding process. Upfront steps are taken to optimize the design so that unwanted quality and reliability issues during qualification and ramp-up phase can be eliminated. With the through gate design the compound flow mechanics and rheology that can create wire sweep, incomplete fill, and compound wettability are thoroughly examines and analyzed before the design is frozen. The upfront analysis on the technical challenges and numerical models are used to predict the interactions between material behavior and the tool designs. The results at qualification and ramp-up showed that molding related issues can be greatly minimized and project timeline can be met. Investment is minimized by designing the frame dimension to the existing machine maximum capacity except trim and form machine.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123394151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal reliability analysis of through-aluminium-nitride-via substrate for high-power LED applications","authors":"C. Lin, K. Chuang, Y. H. Chang, M. Tsai, C. T. Wu, S. Hu","doi":"10.1109/IEMT.2016.7761912","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761912","url":null,"abstract":"For the high-power LED applications, TAV (Through-aluminum-nitride-via) substrate with a high thermal conductivity provides better heat dissipation. However, the high thermal expansion coefficient mismatch between the AlN (Aluminum nitride) and copper film may cause the failure, and thus affect the reliability of TAV substrate. The objective of this study is to evaluate the reliability of TAV substrate by measuring its strength and the thermal stress of Cu/AlN bi-material plate during the thermal loading and then by comparing those experimental results with the finite element simulation. Two reliability tests are used in this study: one is TS (Thermal shock, -40°C/125°C), the other is PCT (Pressure cook test). Also, the strength of AlN material is measured by using three-point bending test and point load test. The reliability results show that TAV substrates have delamination and cracks after TS, but there are no failure being found after PCT. The determined strengths of AlN are 350 and 650 (MPa) from three-point bending test and point load test, respectively. The results of thermal deformation measurement show that the bi-material plate has thermal residual stress change after the solder reflow process, also indicating that a linear finite element model with the stress-free temperature at 80 °C and thermal load at ΔT= -110°C and 45 C can reasonably represent the stress state of the TS test from -40 C to 125 C without considering time-dependent effect. The further results of the finite element simulation associated with strength data of AlN successfully describe those of the reliability test.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120895725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Trade-offs in CAC memory terminations","authors":"Pooja Nukala, V. Adsure, Shu Young Cheah","doi":"10.1109/IEMT.2016.7761985","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761985","url":null,"abstract":"DDR3L based memory bus design conventionally employs termination on the command, address and control bus. This paper discusses the effort to optimize the bus to function within the specifications without these terminations. Signaling and power sensitivities are discussed at various bus speeds.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124320204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal substrates for efficient heat dissipation in LED packaging application","authors":"J. W. Mah, S. Shanmugan, Z. Ong, D. Mutharasu, A. Azmi","doi":"10.1109/IEMT.2016.7761958","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761958","url":null,"abstract":"In recent high power LED applications, metal core PCB (MCPCB) has replaced FR4 PCB in order to achieve greater heat dissipation ability. However, the low thermal conductivity of dielectric and other complicated structures in MCPCB has not supported to maintain junction temperature in safe level when LED is operated at higher power. The challenge is to identify and synthesize high thermal conductivity materials and thin dielectric layers that would favour the usage of MCPCB as a better heat dissipation elements for high power LEDs. This research is focused on developing such thermal substrates with enhanced thermal conductivity at a low cost for mass production. Variety of thin films especially metal oxides and also nitrides as dielectric material (with high thermal conductivities) have been researched rigorously, as these materials could be synthesized as thin films and also as thick films. As a result, the total thickness of thermal substrates could be reduced and hence lower thermal resistance is achievable. In this paper, two different kinds of materials such as ZnO (thick film) and B-AlN (thin film) have been synthesized by two different methods such as screen printing followed by co-precipitation method and chemical vapor deposition using bubbler technique respectively. As an outcome of this research, ZnO thick film was screen printed on Al substrates and cured at low temperatures (125°C) which is low as compared with current curing temperature (>350°C). The screen printed substrates was used as thermal substrates to replace the glassy dielectric material (current practice in industries) of low thermal conductivity. The performance of such thermal substrates were tested using commercial LEDs which has shown a low thermal resistance for pure ZnO thick films with a thickness of 25μm. As observed low thermal resistance with ZnO thick film, the junction temperature of the LED was reduced noticeably. ZnO thick film is also having good reflectivity and can be considered as reflective substrates in electronic packaging. Low curing temperature of the proposed ZnO dielectric paste will also lead to low cost fabrication and mass production of the product. In addition to the above, B-AlN thin film (400 nm) was also deposited by CVD method using gas bubbler on bare Al substrates to improve the performance of thermal substrates (prototype) and compared with commercial MCPCBs. Improved performance of LED was achieved with high value in lux for B-AlN thin films deposited thermal substrates, low thermal resistance and high difference in junction temperature (ATj = 13°C) in comparison with MCPCB. Overall, ZnO thick film and B-AlN thin film deposited Al substrates has been proposed as an alternative to replace commercially available thermal substrates, in place of MCPCBs and FR4s.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"26 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116788863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}