Trade-offs in CAC memory terminations

2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference Pub Date : 2016-09-01 DOI:10.1109/IEMT.2016.7761985

Pooja Nukala, V. Adsure, Shu Young Cheah

引用次数: 0

Abstract

DDR3L based memory bus design conventionally employs termination on the command, address and control bus. This paper discusses the effort to optimize the bus to function within the specifications without these terminations. Signaling and power sensitivities are discussed at various bus speeds.

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在CAC内存终止中的权衡

基于DDR3L的存储总线设计通常在命令、地址和控制总线上使用终端。本文讨论了优化总线以使其在没有这些终端的情况下在规范内工作的努力。讨论了在不同总线速度下的信号和功率灵敏度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference

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