2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference最新文献

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Reliability considerations of sintered silver paste on clip semiconductor packages 夹式半导体封装上烧结银浆料的可靠性考虑
Richard Q. Clemente, Erik Nino Tolentino, M. Azman
{"title":"Reliability considerations of sintered silver paste on clip semiconductor packages","authors":"Richard Q. Clemente, Erik Nino Tolentino, M. Azman","doi":"10.1109/IEMT.2016.7761965","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761965","url":null,"abstract":"Sintered Ag has gained attention as a replacement for high lead applications due to its high thermal, electrical and reliability performance. Today, the temperature requirements for certain business units require higher levels of capability. Coupled with the pressures of converting to lead free, a feasible solution needs to be reached soon. This led to the formation of the DA5 (die attach 5) consortium in 2010. This was composed of semiconductor companies NXP, STMicroelectronics, Freescale, Infineon and Bosch. The main purpose was to look for alternative materials that can support application requirements exceeding the capabilities of solders. Although lab scale tests shows that sinter Ag can be an alternative, limited data is available on sintered Ag performance integrated with high power device applications. Samples were assembled using sinter Ag die attach material on using a Zener diode housed on a clip package. The experimental method was divided in two phases: material characterization at varying amounts of N2 and reliability phase which subjects these units to Temperature Cycle, Highly Accelerated Stress Test (HAST), and Autoclave. All samples underwent normal assembly except for the sintering process which is necessary for silver die attach to achieve solid state diffusion. Microstructure analysis of sinter Ag die attach results into denser formation of sinter Ag paste when subjected to low N2 concentration. Die shear results were highest at low N2 concentration due to increased grain boundary formation over the sinter Ag matrix. However, low N2 concentration leads to copper oxidation which is detrimental on surface adhesion between of the lead frame and mold compound. This was observed during the characterization step wherein oxides were formed on the lead frame surface. Subjecting the copper lead frame with gross oxide formation led to failures at autoclave test. Scanning acoustic tomography reveals gross separation of lead frame to mold compound interface. Also, we have determined that silver migration is a key failure mechanism for sinter Ag die attach when subjected at high N2 concentration. The reliability results for mid and low N2 sintering atmosphere show resistive effect on Ag migration. The overall outlook for Sinter Ag based on the current experimentation suggests that sinter Ag could be a viable solution provided that these key failure mechanisms are addressed and fully understood.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126316396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Redefining IC packages with super-thin Substrates 用超薄基板重新定义IC封装
C. Lee, P. C. Wilson Ang, B. Ang, W. Tan, K. Horng
{"title":"Redefining IC packages with super-thin Substrates","authors":"C. Lee, P. C. Wilson Ang, B. Ang, W. Tan, K. Horng","doi":"10.1109/IEMT.2016.7761933","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761933","url":null,"abstract":"In an industry which demands for continuous innovation and perfection, we are constantly deriving new processes and solutions to break the technological limits which will set us apart. We are striving to achieve denser integrated circuits for better performance as Moore's law perceives and also redefining the word, “Thin”. Driven by cost and in order to achieve thinner IC packages, we have created an innovative solution which enables us to produce ultra-thin substrates. This technology allows us to make use of conventional materials such as PICs(photo imagable coverlay) and merging them with substrates to create products as thin as 25um. Our aim is to showcase the advantages of our Super-thin substrates versus the Molded interconnect substrates in terms of process and capability. This project is done and carried out in QDOS Interconnect.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126821699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Increasing package robustness with palladium coated copper wire 增加包覆钯铜线的封装坚固性
Rodan A. Melanio, Regine B. Cervantes, Sonny E. Dipasupil
{"title":"Increasing package robustness with palladium coated copper wire","authors":"Rodan A. Melanio, Regine B. Cervantes, Sonny E. Dipasupil","doi":"10.1109/IEMT.2016.7761950","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761950","url":null,"abstract":"Alternative solutions to gold wire are being sought as a for lower cost packages. Palladium coated copper (PCC) wires serve as a potential alternative to increase package robustness and lower package cost particularly in the automotive industry. Palladium on the surface of the wire promotes better adhesion of the wire to the surface where it is bonded. In effect, this may result to elimination of broken wire at heel and lifted ball. This paper discusses the material considerations involved in shifting to PCC wire. In this paper, the benefits of coating bare Cu wire with Pd are discussed. These improvements include enhancements in material properties, wirebond responses, intermetallic compound (IMC) formation and reliability that Pd coating imparts on Cu wire. Palladium coating on Cu wire results to better first and second bond reliability hence, improving package robustness.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130001428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Patent landscape and market segments of sintered silver as die attach materials in microelectronic packaging 微电子封装中烧结银贴片材料的专利格局与市场细分
K. Siow, M. Eugenie
{"title":"Patent landscape and market segments of sintered silver as die attach materials in microelectronic packaging","authors":"K. Siow, M. Eugenie","doi":"10.1109/IEMT.2016.7761974","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761974","url":null,"abstract":"Sintered silver (Ag) is a porous silver attaching the semiconductor die to the microelectronic substrates. The market sizes for sintered Ag are explored, and the relevant patents are analyzed at macro and micro-levels. At the macro-level, patenting activity moves to Stage 2 of the technology life-cycle “s-curve”. In stage 2, patenting slows down before the next surge in patenting, likely to be spurred by the wider adoption of wide band-gap semiconductor. The low profitability of sintered Ag also coincides with the available market research reports on the three major market of this technology, i.e., power module, power discrete technology and consumer integrated circuits. However, the patent owners are not abandoning their patents applications. Only eleven entities are co-filing patents related to sintered Ag based on 350 patents and patent applications analyzed here. Such trend suggests the nascent characteristics and continuing investment in this technology. At the micro-level, patenting addresses the following issues. Firstly, pressure assisted sintering is necessary and more reliable than pressureless sintering but the former requires additional process controls and capital investments than the latter. The current state of the art of sintered Ag joint also favours sintering in an ambient environment that oxidizes the substrate. This oxidation poses a delamination risk, and a reliability concern to the microelectronic packages. Lastly, sintered Ag paste favours sintering on the Ag or Au-metallized substrate that represents an additional cost to the customers.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128290360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Customizable silicone materials for MEMS and semiconductor packages 可定制的有机硅材料,用于MEMS和半导体封装
W. Yao, R. Peddi
{"title":"Customizable silicone materials for MEMS and semiconductor packages","authors":"W. Yao, R. Peddi","doi":"10.1109/IEMT.2016.7761976","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761976","url":null,"abstract":"Micro Electro Mechanical Systems (MEMS) are enabling the merger of various sensing capabilities into a single device, and are used in many different applications. Largely employed in the handheld sector, which is driving MEMS growth, smartphones today can contain as many as ten to twelve - or even more - MEMS devices, with this number projected to grow in the coming years. Automotive integration of MEMS is also in the fast lane. Pressure sensors, speed sensors, air flow sensors, GPS systems and accelerometers - all are driven by MEMS and are critical elements to proper automobile function and efficiency. Manufacturing MEMS devices is a balancing act, as MEMS die are very sensitive and fragile. Too much stress from die bonding may crack the die and, if the bonding adhesive's modulus is high, the die can bend due to stress. This flex can cause the moving parts of the MEMS to go out of calibration. To accommodate these stress and modulus challenges, a silicone material technology for MEMS devices which offers a low and stable modulus across the reflow profile has been developed. The material has no bleed and higher adhesion strength than previous-generation adhesives and is completely customizable. The unique Silicone platform has been developed with the freedom to adjust not only the rheological properties, but other key material properties such as modulus as well. Different color samples can also be developed based on product requirements.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120951750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
3D Interconnects — The enabler of next generation multi-Gbps single-ended bus 3D互连-下一代多gbps单端总线的推动者
K. Yong, B. E. Cheah, J. Kong
{"title":"3D Interconnects — The enabler of next generation multi-Gbps single-ended bus","authors":"K. Yong, B. E. Cheah, J. Kong","doi":"10.1109/IEMT.2016.7761908","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761908","url":null,"abstract":"The rising demands of miniaturize and high performance electronic gadgets necessitates higher density with higher bandwidth interconnect which is being limited by prevailing microwave effects as signaling data-rate surges and routing pitch shrinks. This paper presents a transmission line design with three-dimentional (3D) reference plane to alleviate the signaling crosstalk impacts that limit the performance scaling of high-speed parallel bus design such as on-package interconnects (OPI). Simulation result indicates eye opening improvements of >40% for OPI bus operates at 4Gbps data rate is feasibible with the crosstalk reduction achieved through the 3D reference plane design.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132380976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Elimination mold flash by mold design enhancement and leadframe process control on flat power package 通过模具设计改进和引线框架工艺控制,消除平板电源封装模具闪边
Kow Siew Ting, Vishal Kumar, N. Kumar
{"title":"Elimination mold flash by mold design enhancement and leadframe process control on flat power package","authors":"Kow Siew Ting, Vishal Kumar, N. Kumar","doi":"10.1109/IEMT.2016.7761941","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761941","url":null,"abstract":"This paper will explained detail of challenge to eliminate mold flash in mold assist film technology on flat power package. Film assist molding uses a film is coated with an adhesive layer on one side which works as a soft cushion to cover of the heat sink / paddle. This thin film also holds the lead frame paddle for prevention the paddle to tilt. Tilting of the paddle causes the mold to flow towards the paddle area during molding process and causes a reject known as “Pad Bleed”. The flash layer on the heatsink is unable to be removed by typical deflash setting, thus it prevents tin plating coverage during plating process. As a result, the solder-able pad is unable to be mounted at end customers' application circuit. The hypothesis of mold flash occurrence is due to paddle deformation caused by over-clamping during mold process. This paper will emphasis on effectiveness of combining mold design enhancement and lead frame incoming quality control to eliminate mold flash on exposed heatsink flatpower product using film assisted molding system. Distribution clamp force evenly in mold tool is major area to investigate for mold tool design enhancement. Furthermore, process control on supplier to minimize paddle tilting is another main contributor factor need to evaluate in order to maintain incoming quality. By identifying and establishing a control on a critical lead frame dimension and redesigning the mold tool, mold flash or resin bleed was able to be eliminated. The verification run showed paddle tilting is the most critical factor that needs to be controlled in order to minimize resin bleed issue, these thin resin bleed or flashes are able to be removed by the subsequent “Deflashing” process.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131921142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A case study in time-based failure mode and successful mechanism identification by accelerated stress method 基于时间的失效模式及基于加速应力法的成功机理识别实例研究
Joenar Escuro, Eugene Beboso, Erick Gutierrez
{"title":"A case study in time-based failure mode and successful mechanism identification by accelerated stress method","authors":"Joenar Escuro, Eugene Beboso, Erick Gutierrez","doi":"10.1109/IEMT.2016.7761969","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761969","url":null,"abstract":"Automated testing of semiconductor devices has been increasingly more complex in the effort of catching failures in the shortest possible time as part of maintaining the cost competitiveness of the device. Typically entire test programs for medium complexity devices may run in the microseconds. However, what if the failure encountered by the device only manifests after several minutes of continuous operation ? This is also a challenge for semiconductor failure analysis since the failure mode will only occur after a prolonged time of device operation. This paper will discuss a case study wherein the device will fail at the output voltage parameter only after approximately several minutes in continuous biased condition.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122565581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thermal management of LED with vapor chamber and thermoelectric cooling 带蒸汽室和热电冷却的LED热管理
K. S. Ong, C. F. Tan, K. C. Lai, K. Tan, R. Singh
{"title":"Thermal management of LED with vapor chamber and thermoelectric cooling","authors":"K. S. Ong, C. F. Tan, K. C. Lai, K. Tan, R. Singh","doi":"10.1109/IEMT.2016.7761956","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761956","url":null,"abstract":"A fin heat sink (FHS) is a thermal heat transfer device employed to dissipate heat from a high temperature heat source to a lower temperature surrounding. A typical FHS consists of a flat metal base with an array of cooling fins on top. A problem normally encountered in thermal management of electronic packages is thermal heat spreading resistance which occurs as heat flows by conduction from a high temperature heat source to a low temperature heat sink with different cross-sectional areas. As high powered semiconductor chips are made more compact and requiring greater heat dissipation, more effective cooling systems have to be devised. There are various methods employed to minimize this heat spreading resistance. These include increasing the thickness of the base of the FHS or height of the fins. Another method is to use more expensive highly conductive materials like aluminum, copper and diamond which would increase cost. A more economical alternative would be to combine a flat heat pipe (HP) sometimes termed a vapor chamber (VC) with a conventional FHS to increase effective thermal conductivity at the base. Thermoelectric (TE) is the direct conversion of temperature difference between the junctions of two dissimilar materials (thermocouple) to electricity. The converse is true. A voltage applied between the junctions of the thermocouple creates a temperature difference between them. This effect could be utilized as a heat pump to transfer heat from the cold junction to the hot junction. A dc voltage imposed across a thermoelectric (TE) module causes a temperature difference to be imposed across the surfaces of the resulting in one face to be at a temperature higher than the other face. Heat is absorbed from a heat source in contact with the cold surface and dissipated to a heat sink in contact with the hot surface. This paper presents the results of an investigation conducted to evaluate the performance of VCs and TEs for the thermal management of LEDs.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128558939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Defining application spectrum for acrylic based backside tape on QFN leadframes 定义QFN引线框架上丙烯酸底面胶带的应用范围
T. K. Yan, V. Ramalingam
{"title":"Defining application spectrum for acrylic based backside tape on QFN leadframes","authors":"T. K. Yan, V. Ramalingam","doi":"10.1109/IEMT.2016.7761940","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761940","url":null,"abstract":"Constant search of new Bill of Material (BOM) has enable back end manufacturing industry to provide lower die free package cost annually, thus stretching the product lifecycle. A thorough characterization and optimizing the new material behavior in mass manufacturing environment is as important as obtaining life test results of the end product meeting customer requirements. BOM contributing to high in-process yield loss, though with low cost commodity price will defeat the bottom line of reducing die free package cost, as more rework and scrap can be generated. Indirectly, the added screening process will increase operational cost and has higher probability of reject escapee causing customer complaints. In the effort to qualify an alternate source of backside tape with Acrylic based adhesive on QFN leadframes, material characteristic comparison between two adhesive layers on the tape was performed; Olefine Styrene-Ethylene-Butylene-Styrene (SEBS) and Acrylic (Poly-Butyl-acrylate-acrylic-acid). The differences were significant on Coefficient of thermal expansion (CTE) properties, moisture absorption, adhesion strength, and 3D displacement showing warpage level at elevated temperature. The characterization test results were used as a guideline to confirm the behavior of the leadframes while it undergoes series of heating and cooling process at die bond, snap curing, wire bonding before the tape could be removed from the leadframe after molding. In the DOE conducted, leadframe design, wire bond duration and leadframe thickness were varied to ensure the new tape could be used over various leadframe design and leadframe thickness. Besides leadframe, the DOE were used to confirm if it is critical to establish initial curing process step to remove moisture from tape before assembly process. In every process steps, warpage value of the leadframes were measured and inserted back to the magazine to continue to the following processes. The experiment revealed that warpage level was at its highest after wire bonding and remained permanent until the tape was removed. The leadframe design and thickness influences the warpage level, while there was minimal effect of introducing initial curing process and prolonging the wire bonding duration at 225°C. No glue residual were found on the leadframe after detaping that matches to adhesion test after heat treatment. The findings is used to identify robust application spectrum of acrylic based adhesive tape for leadframes in mass scale, while newer tape adhesives continue to be explored.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126300258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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