2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference最新文献

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Innovative of mechanical top clamp fixture calibration through load cell methodology 创新的机械顶夹夹具校准通过称重传感器的方法
Tan Jui Ang, N. Kong
{"title":"Innovative of mechanical top clamp fixture calibration through load cell methodology","authors":"Tan Jui Ang, N. Kong","doi":"10.1109/IEMT.2016.7761942","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761942","url":null,"abstract":"3D imaging module was integrated by 3 Printed Circuit Board Assembly (PCBA) which consists of Main Board (MB), Projector Mini Board (PMB) and 2 Camera Module (2CAM). A piece of thin liner will then attach underneath of the module to strengthen the structure and as heat transfer mechanism. In order to achieve product specification on module thickness and flatness, a mechanical top clamp fixture with plungers was designed to flatten the module during liner assembly prior to curing process. Regular calibration on mechanical top clamp plungers are required in order to maintain a consistency of each plunger force in flattening the module. However, conventional calibration with feeler gauge method is time consuming which required to measure and adjusting the plungers lever to it optimized level. This paper share the new developed calibration method with load cell vs conventional calibration approach, working principle, advantages and result. This innovation have improved 2x top clamp fixture calibrated per day.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128006071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Influence of injection current and ambient temperature on intensity and wavelength of low-power SMD LED 注入电流和环境温度对小功率SMD LED发光强度和波长的影响
M. E. Raypah, M. Devarajan, F. Sulaiman
{"title":"Influence of injection current and ambient temperature on intensity and wavelength of low-power SMD LED","authors":"M. E. Raypah, M. Devarajan, F. Sulaiman","doi":"10.1109/IEMT.2016.7761989","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761989","url":null,"abstract":"Low power surface-mounted (SMD) LEDs are paid much attention in research and development due to their portability and miniaturization. Optical characteristics of SMD LEDs have to maintain more accurate specifications in signaling applications such as traffic lights or railway. Current and temperature stabilization is important for attaining constant spectral properties of SMD LEDs. In this manuscript, the effect of change in ambient temperature and injection current on SMD LED intensity and wavelength shift is reported. Measurements were carried out using a spectrometer to record the LED optical parameters at various operating conditions. Detailed analyses show that the ambient temperature has a significant influence on optical characteristics of low-power SMD LED. The investigation of LED optical behaviors helps in choosing the appropriate working condition at the optimum level.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115441911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Comprehensive study to enable successful probing of GaN wafer technology 全面研究,成功探索GaN晶圆技术
Tang Mee Sean
{"title":"Comprehensive study to enable successful probing of GaN wafer technology","authors":"Tang Mee Sean","doi":"10.1109/IEMT.2016.7761981","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761981","url":null,"abstract":"The power MOSFET wafers which base on silicon substrates are almost reaching end of road, lacking on both performance and cost. It was widely predicted in the industry that next generation wafers should come from Gallium Nitride (GaN) substrate. This new material is expected to be the dominant technology due to its competitive in almost all aspects. Many high power device providers are making deep dive efforts, hopefully to penetrate market earlier than all other competitors. The challenges in achieving that target include facing some of the strangest issues. One of the issues faced in GaN HEMT wafer is not able to perform proper testing as it is a normally-on device. A lot of efforts were invested into developing breakthrough probing process in order to determine quality of device before going into assembly packaging. In the process to develop robust probing methodology, there were many quality occurrences and concerns. Multiple rounds of evaluations were executed and finally obtained few robust options. Upon actual verifications, a new improved probing methodology was selected. It could provide reasonable and reliable measuring performance while concluding new circuits should be redesigned at wafer level. With this new probing method, time to market could reach extremely good performance, enabling competitive advantage in market penetration.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129905176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast and accurate USB2.0 high speed buffer transmit tuning flow 快速准确的USB2.0高速缓冲传输调谐流
Bih Qui Tiang, W. Tan
{"title":"Fast and accurate USB2.0 high speed buffer transmit tuning flow","authors":"Bih Qui Tiang, W. Tan","doi":"10.1109/IEMT.2016.7761990","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761990","url":null,"abstract":"This paper presents an efficient and accurate method flow in USB2.0 high speed buffer tuning. The paper seeks to tackle the issue of lengthy development (pre- & post-silicon design) cycle on determining correct and optimized Analogue Front-End (AFE) buffer register settings for the extensive variation of topologies and wide electrical loss profile channels of USB2.0. A current process flow typically goes through multiple simulation and measurement iterations on the best available settings to pass the eye diagram across the many silicon process, voltage, temperature and impedance corners. The proposed tuning flow can be implemented in an automated algorithm which focuses on examining additional points and electrical parameters in both the 1st & 2nd half of the eye in order to finalize the most optimized settings according to the margins with buffer strength. Of note, this flow maintains a robust accuracy and flexibility where buffer strength are correlated, and algorithms are tested in pre-silicon as well as post-silicon. Ultimately, this translates into an efficient high speed eye diagram tuning capability and enabling a significant saving in time and effort spent on pre-silicon analysis, post-silicon measurement and a shorter design cycle, while maintaining USB2.0 electrical specification compliance in increasingly complex and variant channel solutions.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128751547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Studies on XPS valence state analysis of copper materials 铜材料的XPS价态分析研究
H. Younan, Shen Yue, Li Kai, W. J. Yuan, C. Y. Shen, Chen Yixin, Fu Chao, Li Xiaomin
{"title":"Studies on XPS valence state analysis of copper materials","authors":"H. Younan, Shen Yue, Li Kai, W. J. Yuan, C. Y. Shen, Chen Yixin, Fu Chao, Li Xiaomin","doi":"10.1109/IEMT.2016.7761945","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761945","url":null,"abstract":"XPS analysis technique can be used for valence state analysis. However, due to the limitation of the energy resolution of XPS, it can be difficult to differentiate the valence state of some elements. In this study, the Scanning XPS Microscope PHI Quantera II was used to analyze and identify Cu2O from Cu. Although the equipment possesses good energy resolution (0.48 eV), it is still difficult to distinguish Cu+ from Cu as their difference of the 2p3 energy (0.20 eV) is less than the energy resolution of the XPS tool. In this paper, we will study the method to identify and distinguish Cu+ from Cu by using LMM energy peak in XPS spectra.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130133339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Qualification and application of pressure-less sinter silver epoxy 无压烧结环氧银的鉴定及应用
Loh Kian Hwa, Nadzirah Yahya, Chin Siew Kheong, Lee Ken Hok
{"title":"Qualification and application of pressure-less sinter silver epoxy","authors":"Loh Kian Hwa, Nadzirah Yahya, Chin Siew Kheong, Lee Ken Hok","doi":"10.1109/IEMT.2016.7761938","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761938","url":null,"abstract":"Semiconductor industry is getting momentum to use pressure sinter silver to replace solder on high power application due to need to replace the lead in the solder. But pressure sinter silver epoxy requires heavy investment on the pressure molding and oven cure equipment. The existing pressure sinter silver is also need to dedicated to identified package type and this will causing the package flexibility concern. So, we would like to explore the pressure-less sinter silver epoxy. There are already many paper presented by the semiconductor industry and research centre and still a lots of work need to done in order to qualify this pressure-less sinter silver epoxy. In this paper, we will discuss the collaboration work between supplier and customer to qualify this pressure-less sinter silver epoxy. Now we are understand the behavior of this pressure-less sinter silver epoxy and can predict the application to suit this epoxy.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122948988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An investigation on micro-via drilling on ceramic substrates by a picosecond laser 皮秒激光在陶瓷基板上微孔打孔的研究
H. Hsu, Shih-Jeh Wu
{"title":"An investigation on micro-via drilling on ceramic substrates by a picosecond laser","authors":"H. Hsu, Shih-Jeh Wu","doi":"10.1109/IEMT.2016.7761911","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761911","url":null,"abstract":"Special ceramics are getting more attention as substrate materials for IC packaging, LED packaging and PC board. Certain ceramic materials have high mechanical strength, low thermal expansion, high electric barrier and high thermal conductivity. These properties are idea for devices pf designated purpose such as high power IC, LED and fast communication IC. For these applications via holes for signal and power connection are necessary. As the devices are miniaturized the sizes of via holes are forced to be reduced even down to tens of micrometers, thus, the drilling task can only be performed by laser. However, the ceramics are brittle and during the laser machining process the thermal stress and shock may easily cause defect in the heat affected zone. Also the debris generated in the thermal fusion-solidation process deteriorate the integrity of the via hole such as the in-out diameter, taper angle and roughness around the via. There is a trade-off between machining efficiency and quality has to be tuned. In this paper we apply a 12 picosecond 1033 nm wavelength laser to study the photo material interaction for drilling micro via in three thin plates of AlN, Al2O3 and Fe2O3 ceramic. AlN and Al2O3 are good heat dissipation material and Fe2O3 is idea for electronic noise immunity. A detail report of the results including machining parameters and inspection of via holes will be presented.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132907107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Performance and power implications of decoupling allocation with power gated domains 功率门控域解耦分配的性能和功率影响
C. Kuan, Sameer Shekhar, A. Jain
{"title":"Performance and power implications of decoupling allocation with power gated domains","authors":"C. Kuan, Sameer Shekhar, A. Jain","doi":"10.1109/IEMT.2016.7761984","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761984","url":null,"abstract":"Gated power delivery network (PDN) system design requires careful decoupling capacitor allocation between ungated and gated loads. This paper illustrates the pros and cons of ungated and gated capacitors to system performance based on impedance and latency characterization. Solution with only ungated decoupling gives power benefits whereas gated decoupling provides optimized performance but larger latency. Simulations of microprocessor packages are used to illustrate challenges and decision factors.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132227621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and characterization of thermal conductive wafer coating in thin small outline package for automotive product application 汽车产品小轮廓薄型封装导热晶圆涂层的设计与表征
A. Hamid, Dhanapalan Periathamby, Suhaimi Azizan, C. E. Tan, S. Nadarajan
{"title":"Design and characterization of thermal conductive wafer coating in thin small outline package for automotive product application","authors":"A. Hamid, Dhanapalan Periathamby, Suhaimi Azizan, C. E. Tan, S. Nadarajan","doi":"10.1109/IEMT.2016.7761955","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761955","url":null,"abstract":"The thermal conductive die attach (DA) material is very important component and it is function to create a joint between die and leadrame as well as to dissipate heat from die throughout the package. However, the dispensing DA material is giving problems, which is epoxy overflow, die tilted especially when dealing with small die size (ranging 15 to 30 mils). Because of this problem, industries are using noncon-ductive dispensing epoxy without metal content and resulting good for manufacturing. There is another problem when using nonconductive epoxy which reducing in thermal and performance of the device. In this paper, we presents conductive material coated at backside of wafer (conductive WBC) and giving excellent thermal and device performance and good for integrated device assembly manufacturing. In the most stringent automotive application, device performance is critical to component level. The small and thin die assembled in Thin Small Outline Package (TSOP), good thermal conductive die attach material is required, together with excellent robustness in oxidation control, manufacturability and reliability. Upon completion of multiple material screening, wafer back coating (WBC) material had selected. It is thermal conductivity can reach approximately 2.2-W/mK and which is enough for lower power devices as well as good in thermal conductivity. With all the improved assembly processes, conductive wafer coated material achieved good manufacturability, excellent thermal performance, meeting customer specification and ready for high volume manufacturing.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128047454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of Cu based complexes on EFTECH 64 and C194 Cu alloy Cu基配合物对EFTECH 64和C194 Cu合金的影响
C. Ong, K. Lau, M. Zaimi, Kim-Swee Goh, M. Tay
{"title":"Effect of Cu based complexes on EFTECH 64 and C194 Cu alloy","authors":"C. Ong, K. Lau, M. Zaimi, Kim-Swee Goh, M. Tay","doi":"10.1109/IEMT.2016.7761982","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761982","url":null,"abstract":"Cupric chloride etchant was used to removing the unwanted copper alloy carrier of molded units' strips and to expose the Ni bump interconnects. However, an uncontrolled etching process of the carrier led to rough Ni bumps' surface, contributing to cosmetic defect and poor electroless Ni plating's shear strength. The current paper investigates the effect of pH, Cu specific gravity and etching speed using cupric chloride-based etchant on the surface roughness of Ni bumps after the etching of respective EFTECH-64-or C194-grade Cu alloy carriers. The DOE input factors on Cu alloy were established with the help of CEDA software. The alkaline etching of C194 resulted in a higher Ni bump's surface roughness as compared to the EFTECH-64 etching. However, under low pH and high specific Cu density parameters, C914 etching produced low surface roughness which comparable to the EFTECH-64 sample due to the consistency of resulted bump's surface roughness at upper and lower levels of etching parameters.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131533441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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