Fast and accurate USB2.0 high speed buffer transmit tuning flow

This paper presents an efficient and accurate method flow in USB2.0 high speed buffer tuning. The paper seeks to tackle the issue of lengthy development (pre- & post-silicon design) cycle on determining correct and optimized Analogue Front-End (AFE) buffer register settings for the extensive variation of topologies and wide electrical loss profile channels of USB2.0. A current process flow typically goes through multiple simulation and measurement iterations on the best available settings to pass the eye diagram across the many silicon process, voltage, temperature and impedance corners. The proposed tuning flow can be implemented in an automated algorithm which focuses on examining additional points and electrical parameters in both the 1st & 2nd half of the eye in order to finalize the most optimized settings according to the margins with buffer strength. Of note, this flow maintains a robust accuracy and flexibility where buffer strength are correlated, and algorithms are tested in pre-silicon as well as post-silicon. Ultimately, this translates into an efficient high speed eye diagram tuning capability and enabling a significant saving in time and effort spent on pre-silicon analysis, post-silicon measurement and a shorter design cycle, while maintaining USB2.0 electrical specification compliance in increasingly complex and variant channel solutions.