2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference最新文献

{"title":"The process characterization of insulated Au-Flash PdCu for the challenging wire bonding applications","authors":"S. C. Teck, E. P. Leng, T. Chu, Zhang Xi, Loh Wan Yee, Su Dan, T. C. Wei","doi":"10.1109/IEMT.2016.7761951","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761951","url":null,"abstract":"With the success of developing insulated wire bond recipe in the conventional wire bond process for ball grid array (BGA) and quad flat package (QFP). The development of insulated wire bond process is moving further to explore into other areas of bonding applications with potential challenges on insulated Au-Flash PdCu wire. At the same time, the characterization process was perform on the insulation coating thickness in order to establish an optimize insulation thickness. The thickness of the insulation layer becomes more critical when it apply into wider areas of bonding applications. In fine pitch and critical wire bond process, any variations to either the insulation coating layer itself or the bonding processes used could affect the overall stability and bondability of insulation wire. Series of assessments were performed to assess the performance of various insulation thicknesses in terms of wire bondability, electrical insulation and wire bond quality. Eventually, a new insulation thickness window in terms of break down voltage (BDV) was established that able to fulfill all the requirements. One critical potential area of study for insulated wire would be in Ultra-Low-Loop (ULL) application down to 2mils loop height. Since at such low loop height, the critical loop bendings would occur at the bonded ball neck region which is subjected to the high energy effects during EFO sparking, this could result in regional peeling-off of the insulation coating on the wire due to the partial breaking down or weakening of the insulation layer and bending stresses incurred at the ball neck region. Thicker insulation coating may complicate ULL applications further as this would mean sharp bending through thicker coating material with little ductility. Uneven wire surface contact with the capillary internal walls also sets in and thus resulted in the regional insulation material peeling as illustrated in the paper. Various loop profiles were also studied to assess for any improvements to the ULL application. Another challenging application of insulated wire would be in conventional stitch bond on bump process. The bumped ball smoothing action could result in excessive accumulation of insulation material at the capillary tip, thus causing fast-clogging of the capillary which means an increase in the production costs due to a shorter capillary life-span. This is even so when the insulation coating layer gets thicker. At the same time, insulation material residue that was left on the bumped ball surface prior to the 2nd bond adhesion could result in poor bondability and workability of the stitch bond on bump process. Besides, the flexibility of the insulated wire which enables the criss-crossing wire layout has been fully adopted into a universal substrate concept for the ball grid array (BGA) packaging. The idea is to use one standard substrate design and caters to multiple devices / products. In this case, insulated wire bonds are assigned freely as device ","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116246838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A polymer-made 3DOF spatial parallel manipulator for cell production system","authors":"M. Horie","doi":"10.1109/IEMT.2016.7761954","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761954","url":null,"abstract":"In the present paper, in order to realize the functions equivalent to the functions of the spherical bearing which is frequently used in conventional spatial mechanisms, a polymeric manufactured hinge with Hytrel® (DUPONT Co., Ltd.)[1], which has excellent flexural fatigue resistance, have been proposed. Next, the shape and dimensions of the polymeric manufactured hinge having low stress values at bending deformation have been found by FEM analysis results. In addition, a polymer-made three-degrees-of-freedom(3DOF) spatial parallel manipulator which consists of this polymer-made hinge is designed and developed, and the output displacement characteristics of the manipulator are revealed.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"450 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122824131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Palladium coated copper wire wedge integrity to withstand extended high temperature storage stress test","authors":"L. Chia, Tan Kim Guan, C. Lam, Mak Chee Hoe, Gwee Hoon Yen","doi":"10.1109/IEMT.2016.7761961","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761961","url":null,"abstract":"Copper (Cu) wire bonding technology had been widely accepted as a interconnect material in semiconductor packaging. The main advantage of Cu as a interconnect material is cost, thermal and electrical performance as compare to gold. However effect of corrosive elements on bare Cu wire remain a big challenge for the reliability of Cu wire packages. Market trend is pushing for Palladium coated copper (PCC) wire to be the alternative for bare Cu wire, due to the better bondability process and resistance to corrosive elements. Nevertheless there are many researches suggest PCC wire is not suitable for High Temperature Storage (HTS) reliability stress test more than 150oC due to the intrinsic degradation of PCC wire. From literature review the main contribution to the degration of PCC wire was due to the crack or void on the Palladium (Pd) coating. Cu underneath the Pd coating will diffuse through the crack to the surface and weaken the integrity of the wire. Through sparking parameter optimization, optimal Pd coverage on the FAB can be achieved hence first bond integrity can be secured. On the other hand, 100% Pd coverage on the second bond wedge is impossible to obtain due to the extensive mechanical contact of capillary on the wedge during formation. In this paper, the study will focus on the wedge PCC wire on roughen leadframe with NiPdAuAg surface finishing. The study will cover difference 3 main factors influencing the integrity of wedge, i) wedge formation, ii) leadframe AuAg plating thickness iii) ionic elements from mold compound. Sample with various wedge formation on different AuAg plating thickness with and without mold compound will be subjected to HTS 200oC up to 900 hours and comparison of the degration rate for different samples can be identify. The aim of the study is to identify the dominant factor of the PCC wedge degration on HTS stress so that improvement for package beyond AEC Q100 Grade 0 can be achieved.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116867035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Contact resistance of the micro bumps in a typical TSV structure","authors":"B. Lwo, C. Teng, Tom Ni, Shirley Lu","doi":"10.1109/IEMT.2016.7761906","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761906","url":null,"abstract":"Contact resistance of the micro bumps in a PBGA (Plastic Ball Grid Array) packaging with TSV (Through Silicon Via) structure was characterized in this study. To this end, a self-designed TSV daisy chain circuit was proposed as the measurement paths and the test samples were made with commercialized packaging process to simulate real product behavers. Based on circuit model analysis, contact resistance for the micro bump were extracted from a systematic experimental design and measurement.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116895868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electromagnetic behaviour of flexible substrates with meshed and conductive films ground planes","authors":"M. D. Rotaru, S. H. Pu, A. Kumar, C. W. Mok","doi":"10.1109/IEMT.2016.7761909","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761909","url":null,"abstract":"In this work the electromagnetic performance at high frequency of flexible substrates with meshed and conductive film ground planes is compared with that of flexible substrates with unmeshed (solid) ground planes. Several types of specially designed structures have been studied - mesh ground, conductive film ground and solid copper ground. The conductive film used in this work is based on Tatsuta silver film which is developed especially for flex interconnects to be used in hinge applications in smart phones, and LCD drivers. The flat and bend cases of the flexible substrate are also compared and reported in this work. The comparison is done in frequency domain as well as in time domain through simulation. The structures are compared in terms of their far-field radiation as well as near-field coupling. The simulations have shown that the meshed and conductive film ground will affect the near-field coupling and the loss of the transmission structures but there is little difference in terms of radiating field.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115428520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced packaging and electronic assembly cleaning fluid innovation","authors":"M. Bixenman, J. Chan, T. C. Loy","doi":"10.1109/IEMT.2016.7761975","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761975","url":null,"abstract":"The miniaturization of modern electronics decreases conductor widths, which can create higher risk to insulation failure. As distances between conductors reduce, electronic hardware is more vulnerable to insulation failure, higher voltage gradients and easier to form a corrosion cell. Interconductor spacing influences the migration rate and is inversely related with conductor width. Acceleration factors create multiple stresses due to activation energy, temperature, humidity and voltage. Removal of process residues is needed to reduce electrochemical migration. Cleaning electronic hardware is well known. The challenges with cleaning highly dense hardware are many. Low standoff gaps prevent flux outgassing and can underfill the bottom termination with active flux residue. Mixed metals can react with alkaline cleaning agents, which can result in galvanic corrosion. The time and energy needed to reach the residue and remove contamination under the component requires high pressure spray impingement and increased wash time. The purpose of this research is to present aqueous cleaning technology innovations to address the challenges of cleaning highly dense electronic hardware. Material compatibility on mixed metals, cleaning performance and bath life studies will be presented.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126906899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rate-dependent responses of electroless plated and sputtered copper layer during nanoindentation loading","authors":"M. Afripin, N. A. Fadil, M. F. Hamid, C. Yoon, B. E. Cheah, B. A. Razak, M. Tamin","doi":"10.1109/IEMT.2016.7761957","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761957","url":null,"abstract":"A thin copper layer is an integral part of a Through-Silicon via (TSV) structure. The copper layer experiences mechanical stressing through the temperature excursion, thus raising reliability concern of the component. Such reliability assessment calls for the determination of the mechanical properties of the thin layer. In this respect, this paper discusses the experimental study to establish the loading rate-dependent behavior of the Cu layer deposited on SiO2-coated Si substrate. A series of nanoindentation tests are performed on sputtered and electroless plated copper layer. The tests cover a range of probe displacement rates from 80-400 nm/s and indentation depths up to 400 nm. Load-displacement (depth) data pairs are recorded for each test. Results show that an indentation depth of 3% of the Cu layer thickness is sufficient to eliminate the effect of surface morphology on the indentation load-displacement response. The load-displacement response of the electroless plated copper layer significantly decreases with the test speed, while a minor increase in similar effect is observed for the sputtered layer. The elastic modulus of both the electroless and sputtered copper layer is insensitive to the displacement rates up to 320 nm/s, while the hardness measure of the electroless copper layer linearly decreases with increasing rates.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121997661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Understanding the effect of molding compound mechanical properties on the electrical performances drift of hall effect sensor","authors":"Nadzirah Yahya, R. Krishnan, K. Loh","doi":"10.1109/IEMT.2016.7761986","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761986","url":null,"abstract":"The innovative technology of hall effect sensor (HES) has proven to reach new level in electronic industry. However, it is undeniable that new technology also needs time to be developed into the perfect product. The hall sensor had experienced some issues related to the electrical performance. Several possible factors such as IC design, humidity, delamination, compound visco-elastic property, thermal aging and die attach glue have been included as the cause to this problem. Research studies collaboration between Carsem (M) Sdn. Bhd. and Customer Z was achieved in order to understand the relationship between the electrical performance of hall sensor and the mechanical properties of molding compound. Thermal hysteresis test by Customer Z resulted in sensitivity drift approximately more than 1.5%. The shifts in the hysteresis cycle indicate that the HES is experiencing internal stress from the package. Two types of mold compound were tested in Carsem Technology Centre (CTC) Material Lab at Carsem (M) Sdn Bhd under different post mold cure condition. These mold compound thermal and mechanical properties was determined using in-house lab equipment such as thermal mechanical analyzer (TMA) and dynamic mechanical analyzer (DMA). This technical paper will explore the new method used to predict mold compound stability using TMA equipment and its correlation with the thermal hysteresis of the electrical sensitivity drift. Other testing such as thermal aging, stress relaxation by DMA equipment and moisture absorption test will be further discussed as we conclude the most suitable mold compound to be used in the production of HES package.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126419995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Measurement of the strength of a grain boundary in electroplated copper thin-film interconnections by using micro tensile-test","authors":"T. Shinozaki, T. Nakanishi, K. Suzuki, H. Miura","doi":"10.1109/IEMT.2016.7761963","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761963","url":null,"abstract":"In this study, a micro tensile test method that can measure the interface strength of a grain boundary has been developed by applying an EBSD (Electron Back-Scatter Diffraction) method and a FIB (Focused Ion Beam) system, and it was applied to evaluate the effect of the crystallinity of a grain boundary on the strength of electroplated copper thin films quantitatively. The position and crystallinity of a grain boundary in a polycrystalline electroplated copper thin film were preliminarily determined by EBSD method, and the micro scale test specimen was cut out from the appropriate area in the film by using FIB. Therefore, a bicrystal sample which consisted of the characterized single grain boundary was cut from a polycrystalline thin film, and the strength of one grain or one grain boundary was measured quantitatively. In this study, the crystallinity of grains and grain boundaries was evaluated by using Image Quality (IQ) value obtained from the EBSD method. As a result, the fracture mode and strength of the polycrystalline copper thin films were found to vary drastically depending on the crystallinity of the grain boundary. The specimens including a grain boundary with average IQ value lower than 3500 showed brittle fracture at the grain boundary. On the other hand, in the specimens with average IQ value higher than 3500 showed ductile transgranular fracture. In addition, it was confirmed that the strength of a grain boundary with average IQ value lower than 3500 decreased with decreasing the IQ value and the yield strength of a grain decreased with increasing the average IQ value of a grain. It is, therefore, very important to control the crystallinity for assuring the stable and reliable operation of thin film devices using the electroplated copper interconnections.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130710176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Predictive method for simultaneous switching output jitter of DDR for FPGA","authors":"W. L. Lee, M. Chin, W. Choo, C. Chee","doi":"10.1109/IEMT.2016.7761972","DOIUrl":"https://doi.org/10.1109/IEMT.2016.7761972","url":null,"abstract":"Memory system level Simultaneous Switching Output (SSO) timing variation analysis requires a significantly large amount of simulation time and computing resource. Double Data Rate Synchronous Dynamic Random Access Memory (DDR DRAM) signal integrity analysis requires a complex model that includes numerous data signals, package routing model and Power Delivery Network (PDN) models. Besides, signal analysis and optimization requires multiple simulation iterations. Generally, Field Programmable Gate Array (FPGA) comes in a package matrix where one FPGA device has a few different package types of Input/output (I/O) counts and DDR counts to suit its application. Hence, FPGA needs a long SSO analysis time to cover these package variations. This resulted in a long product cycle time for FPGA. This paper discusses a methodology to build a predictive tool for DDR's SSO noise estimation based on IO mutual inductance (L) coupling and PDN performance calculations of different packages. The test vehicle used was a low cost FPGA with DDR3 600Mbps of x16 DQ in a wirebond package. The correlation between the SSO predictive tool and characterization measurement is also discussed in this paper.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133872592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}