The process characterization of insulated Au-Flash PdCu for the challenging wire bonding applications

Abstract

With the success of developing insulated wire bond recipe in the conventional wire bond process for ball grid array (BGA) and quad flat package (QFP). The development of insulated wire bond process is moving further to explore into other areas of bonding applications with potential challenges on insulated Au-Flash PdCu wire. At the same time, the characterization process was perform on the insulation coating thickness in order to establish an optimize insulation thickness. The thickness of the insulation layer becomes more critical when it apply into wider areas of bonding applications. In fine pitch and critical wire bond process, any variations to either the insulation coating layer itself or the bonding processes used could affect the overall stability and bondability of insulation wire. Series of assessments were performed to assess the performance of various insulation thicknesses in terms of wire bondability, electrical insulation and wire bond quality. Eventually, a new insulation thickness window in terms of break down voltage (BDV) was established that able to fulfill all the requirements. One critical potential area of study for insulated wire would be in Ultra-Low-Loop (ULL) application down to 2mils loop height. Since at such low loop height, the critical loop bendings would occur at the bonded ball neck region which is subjected to the high energy effects during EFO sparking, this could result in regional peeling-off of the insulation coating on the wire due to the partial breaking down or weakening of the insulation layer and bending stresses incurred at the ball neck region. Thicker insulation coating may complicate ULL applications further as this would mean sharp bending through thicker coating material with little ductility. Uneven wire surface contact with the capillary internal walls also sets in and thus resulted in the regional insulation material peeling as illustrated in the paper. Various loop profiles were also studied to assess for any improvements to the ULL application. Another challenging application of insulated wire would be in conventional stitch bond on bump process. The bumped ball smoothing action could result in excessive accumulation of insulation material at the capillary tip, thus causing fast-clogging of the capillary which means an increase in the production costs due to a shorter capillary life-span. This is even so when the insulation coating layer gets thicker. At the same time, insulation material residue that was left on the bumped ball surface prior to the 2nd bond adhesion could result in poor bondability and workability of the stitch bond on bump process. Besides, the flexibility of the insulated wire which enables the criss-crossing wire layout has been fully adopted into a universal substrate concept for the ball grid array (BGA) packaging. The idea is to use one standard substrate design and caters to multiple devices / products. In this case, insulated wire bonds are assigned freely as device specific trace routings in substrates are not required. This idea able to reduce substrate design cycles and at the same time lowers the substrate unit cost. The development performed by NXP with the use of insulated wire has demonstrated good wire bond process feasibility without any major process issue. In summary, the development on various wire bond technologies with insulated wire has widen the application of insulated wire. Detailed wire bond process optimization and characterization successfully improve the feasibility of new insulated wire bond technology. This indicates another great leap in the insulated wire bond application.