{"title":"Crack die elimination by comprehensive optimization throughout all assembly process steps","authors":"W. L. Chin, C. E. Tan, Norsholiha Mohd Shauffi","doi":"10.1109/IEMT.2016.7761943","DOIUrl":null,"url":null,"abstract":"Over years, the crack die defect was proven cannot be screened effectively through Final Test, therefore it has high risk reaching the end applications. This issue can affect many devices, including some miniature devices such as Small Outline Transistors, SOTXXX Eutectic. In order to eliminate the die crack defect, entire assembly process required optimization; including Saw, Die Attach, Wire Bond, Mold, Plating, Trim/Form and Final Test. Each process step has its own risks and therefore full analysis was conducted on all the possible opportunities. At wafer sawing process, several sawing methods were evaluated, including single cut, step cut, 3 channels cutting, cutting directions and selection of various blade types. With the optimum sawing process, die chipping was minimized to lowest level (only few microns), that resulting to minimum die cracking risk. With that performance, further risk investigation was carried on to understand the stress amount inside the package. There were 2 significant stress factors, die location on flag and trim/form impact to the leads. In order to minimize the effect of the stress, die was attached to the location with the least amount of stress. As for trim/form, this involved new design leadframe fabricated and experimented in production. The leadframe design optimization was completed after compliance to the reasonable stress level, as calculated in the trim/form stress analysis. When new leadframe was subjected to actual trim/form process, actual performance was verified by reliability testing. With the optimum assembly configurations, further safety action was depended to the Final Test capability. There were 2 additional test parameters added to increase effectiveness of screening potential die crack rejects. With the total compilation of all the optimum assembly and test configurations, actual performance monitoring showed total elimination of die crack occurrence. This project becomes good benchmark of any die crack reduction or elimination project.","PeriodicalId":237235,"journal":{"name":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 37th International Electronics Manufacturing Technology (IEMT) & 18th Electronics Materials and Packaging (EMAP) Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.2016.7761943","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Over years, the crack die defect was proven cannot be screened effectively through Final Test, therefore it has high risk reaching the end applications. This issue can affect many devices, including some miniature devices such as Small Outline Transistors, SOTXXX Eutectic. In order to eliminate the die crack defect, entire assembly process required optimization; including Saw, Die Attach, Wire Bond, Mold, Plating, Trim/Form and Final Test. Each process step has its own risks and therefore full analysis was conducted on all the possible opportunities. At wafer sawing process, several sawing methods were evaluated, including single cut, step cut, 3 channels cutting, cutting directions and selection of various blade types. With the optimum sawing process, die chipping was minimized to lowest level (only few microns), that resulting to minimum die cracking risk. With that performance, further risk investigation was carried on to understand the stress amount inside the package. There were 2 significant stress factors, die location on flag and trim/form impact to the leads. In order to minimize the effect of the stress, die was attached to the location with the least amount of stress. As for trim/form, this involved new design leadframe fabricated and experimented in production. The leadframe design optimization was completed after compliance to the reasonable stress level, as calculated in the trim/form stress analysis. When new leadframe was subjected to actual trim/form process, actual performance was verified by reliability testing. With the optimum assembly configurations, further safety action was depended to the Final Test capability. There were 2 additional test parameters added to increase effectiveness of screening potential die crack rejects. With the total compilation of all the optimum assembly and test configurations, actual performance monitoring showed total elimination of die crack occurrence. This project becomes good benchmark of any die crack reduction or elimination project.