2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)最新文献_第2页

W/WN/poly gate implementation for sub-130 nm vertical cell DRAM 130 nm以下垂直单元DRAM的W/WN/多栅极实现

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934932

R. Malik, L. Clevenger, I. McStay, O. Gluschenkov, W. Robl, P. Shafer, G. Stojakovic, W. Yan, M. Naeem, R. Ramachandran, K. Wong, J. Prakash, W. Kang, Y. Li, R. Vollertsen, A. Strong, W. Bergner, R. Divakaruni, G. Bronner

引用次数: 2

Deep sub-micron CMOS device design for low power analog applications 低功耗模拟应用的深亚微米CMOS器件设计

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934960

H. Deshpande, B. Cheng, J. Woo

引用次数: 9

Highly scalable sub-10F/sup 2/ 1T1C COB cell for high density FRAM 高度可扩展的低于10f /sup 2/ 1T1C COB电池，用于高密度FRAM

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934974

S.Y. Lee, H.H. Kim, D. Jung, Y.J. Song, N. Jang, M.K. Choi, B.K. Jeon, Y.T. Lee, K.M. Lee, S. Joo, S.O. Park, K. Kim

{"title":"Highly scalable sub-10F/sup 2/ 1T1C COB cell for high density FRAM","authors":"S.Y. Lee, H.H. Kim, D. Jung, Y.J. Song, N. Jang, M.K. Choi, B.K. Jeon, Y.T. Lee, K.M. Lee, S. Joo, S.O. Park, K. Kim","doi":"10.1109/VLSIT.2001.934974","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934974","url":null,"abstract":"Recently, technology innovation for high density and high performance FRAM has been pronounced. Among the breakthrough technologies for high density and high performance FRAM, 1T1C capacitor-on-bitline (COB) cell technology is essential because it can greatly reduce FRAM cell size compared to previous and current 2T2C FRAMs (Kinam Kim, 1999; Lee et al., 1999). Design improvement for enhanced sensing ability is also a promising technology for highly reliable mega-bit density FRAM (Jeon et al, 2000). Although the recent demonstration shows a promising future for stand-alone FRAM applications, current 1T1C COB FRAM still has incomparably large cell size factor compared to DRAM and flash. This is one of the most challenging issues that FRAM faces for developing high-density stand-alone memory. In this work, a novel cell structure for sub-10 F/sup 2/ cell size is for the first time developed. The key technologies for the sub-10 F/sup 2/ novel cell are: (1) advanced oxidation barrier and PZT film technologies which enables MIM ferroelectric capacitors to be lowered to /spl sim/500 nm thick stack: (2) single-mask capacitor etching technology which can produce >80/spl deg/ ferroelectric capacitor fence slope; (3) no cell via contact technology by which capacitor pitch can ideally be reduced to 2F; (4) an Al-reflow process which enables sub-0.4 /spl mu/m back-end interconnection without degrading the ferroelectric capacitor. The novel cell is demonstrated with an experimental 4 Mb FRAM, where the 1T1C COB cell is fabricated with folded bit line architecture and plate line-up sensing scheme.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"107 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131386366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

MOS devices with high quality ultra thin CVD ZrO/sub 2/ gate dielectrics and self-aligned TaN and TaN/poly-Si gate electrodes 具有高质量超薄CVD ZrO/sub /栅极介质和自对准TaN和TaN/多晶硅栅极的MOS器件

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934987

C. Lee, Y.H. Kim, H. Luan, S.J. Lee, T. Jeon, W. Bai, D. Kwong

引用次数: 18

Dopant penetration effects on polysilicon gate HfO/sub 2/ MOSFET's 掺杂剂对多晶硅栅极HfO/sub / MOSFET的渗透效应

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934984

K. Onishi, L. Kang, R. Choi, E. Dharmarajan, S. Gopalan, Y. Jeon, C. Kang, B. Lee, R. Nieh, J.C. Lee

引用次数: 29

High-density and high-performance 6T-SRAM for system-on-chip in 130 nm CMOS technology 高密度、高性能的6T-SRAM，采用130纳米CMOS技术

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934971

W. Kong, R. Venkatraman, R. Castagnetti, F. Duan, S. Ramesh

引用次数: 12

Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide 晶圆取向对直接隧道氧化栅CMOS性能和可靠性的影响研究

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934955

H. Momose, T. Ohguro, S. Nakamura, Y. Toyoshima, H. Ishiuchi, H. Iwai

引用次数: 9

Electron wavefunction penetration into gate dielectric and interface scattering-an alternative to surface roughness scattering model 电子波函数穿透栅极介质和界面散射-表面粗糙度散射模型的替代方案

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934942

I. Polishchuk, C. Hu

引用次数: 13

Retention time improvement by fast-pull and fast-cool (FPFC) ingot growing combined with proper arrangement of subsequent thermal budget for 0.18 /spl mu/m DRAM cell and beyond 通过快速拉伸和快速冷却(FPFC)铸锭生长，结合正确安排0.18 /spl mu/m DRAM单元的后续热预算，提高保留时间

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934981

Kim Ilgweon, Kwon Jaesoon, Lee Kyosung, Kim Dongchan, Shin Jungho, Choy Junho, Kim Namsung, Yang Heesik, Cheon Youngil, Park Juseok, Kwon Woyup, Song Youngjin, Park Daeyoung, Kim Jibum

引用次数: 0

High-performance 157 nm resist based on fluorine-containing polymer 基于含氟聚合物的高性能157纳米抗蚀剂

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934935

S. Kishimura, M. Endo, M. Sasago

引用次数: 1