2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)最新文献_第3页

Electrical characteristics of TaSi/sub x/N/sub y/ gate electrodes for dual gate Si-CMOS devices 双栅Si-CMOS器件的TaSi/sub x/N/sub y/ gate电极的电学特性

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934940

You-Seok Suh, G. Heuss, H. Zhong, Shin-Nam Hong, V. Misra

引用次数: 15

Strained Si NMOSFETs for high performance CMOS technology 用于高性能CMOS技术的应变Si nmosfet

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934946

K. Rim, S. J. Koester, Michael J. Hargrove, J. Chu, Patricia M. Mooney, John A. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill, Hon-Sum Philip Wong

引用次数: 139

A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor 一种基于0.15 /spl mu/m逻辑的嵌入式DRAM技术，采用MIM(金属-绝缘体-金属)电容器，具有0.425 /spl mu/m/sup 2/堆叠单元

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934931

M. Takeuchi, K. Inoue, M. Sakao, T. Sakoh, T. Kitamura, S. Arai, T. Iizuka, T. Yamamoto, H. Shirai, Y. Aoki, M. Hamada, R. Kubota, S. Kishi

引用次数: 2

High performance sub-60 nm SOI MOSFETs with 1.2 nm thick nitride/oxide gate dielectric 高性能60nm以下SOI mosfet, 1.2 nm厚氮化物/氧化物栅极电介质

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934952

W. Maszara, S. Krishnan, Q. Xiang, M. Lin

引用次数: 3

Highly manufacturable and high performance SDR/DDR 4 Gb DRAM 高度可制造和高性能SDR/DDR 4gb DRAM

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934920

K.N. Kim, H. Jeong, W.S. Yang, Y. Hwang, C. Cho, M. Jeong, S. Park, S. Ahn, Y. Chun, S. shin, J. Park, S.H. Song, J.Y. Lee, S. Jang, C.H. Lee, J. Jeong, K. Cho, H. Yoon, J. Jeon

{"title":"Highly manufacturable and high performance SDR/DDR 4 Gb DRAM","authors":"K.N. Kim, H. Jeong, W.S. Yang, Y. Hwang, C. Cho, M. Jeong, S. Park, S. Ahn, Y. Chun, S. shin, J. Park, S.H. Song, J.Y. Lee, S. Jang, C.H. Lee, J. Jeong, K. Cho, H. Yoon, J. Jeon","doi":"10.1109/VLSIT.2001.934920","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934920","url":null,"abstract":"A 4 Gb SDR/DDR DRAM is fabricated with 0.11 /spl mu/m CMOS technology. To the best of our knowledge, this is the first working DRAM ever achieved at such a high density. The cell size and chip size of the 4 Gb DRAM are approximately 0.1 /spl mu/m/sup 2/ and 645 mm/sup 2/, respectively. The key technologies developed for this 4 Gb DRAM are KrF lithography with RET, novel ILD gap-filling, full SAC with LSC, novel W-BL, low-temperature Al/sub 2/O/sub 3/ MIS capacitor, and triple level CVD-Al interconnection technology. The key features of these technologies were reported elsewhere (Jeong et al., Tech. Digest of IEDM, pp. 353-6, 2000). The summary of 0.11 /spl mu/m DRAM technology is listed and compared with our previous 0.13 /spl mu/m (Kim et al., 2000) and 0.15 /spl mu/m (Kim et al., 1998) generations. We have found that random single-bit and/or twin-bit failures and block failures are the most critical issues to be solved for achieving good functionality of 4 Gb DRAM. In order to get rid of the single and twin bit failures, 80 nm array transistors, sub-80 nm memory cell contacts and mechanically robust capacitors are developed and triple-level CVD Al technology is optimized to reduce block failure as well as improve chip performance. In this paper, these technologies for achieving good functionality with high performance are highlighted in detail.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114247527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

High-quality ultra-thin HfO/sub 2/ gate dielectric MOSFETs with TaN electrode and nitridation surface preparation 高品质的超薄HfO/sub - 2/栅极介电mosfet与TaN电极和氮化表面制备

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934924

R. Choi, C. Kang, B. Lee, K. Onishi, R. Nieh, S. Gopalan, E. Dharmarajan, J.C. Lee

引用次数: 47

Radical nitridation in multi-oxide process for 100 nm generation CMOS technology 100纳米一代CMOS多氧化物工艺中的自由基氮化

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934958

Y. Yasuda, N. Kimizuka, K. Watanabe, T. Tatsumi, A. Ono, K. Fukasaku, K. Imai, N. Nakamura

引用次数: 1

A heteroepitaxial MIM-Ta/sub 2/O/sub 5/ capacitor with enhanced dielectric constant for DRAMs of G-bit generation and beyond 一种具有增强介电常数的异质外延MIM-Ta/sub 2/O/sub 5/电容器，用于g位及以上的dram

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934937

M. Hiratani, T. Hamada, S. Iijima, Y. Ohji, I. Asano, N. Nakanishi, S. Kimura

引用次数: 10

Non-uniform chip-temperature dependent signal integrity 非均匀芯片温度相关的信号完整性

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934991

A. Ajami, K. Banerjee, Massoud Pedram

引用次数: 9

Realization of high performance dual gate DRAMs without boron penetration by application of tetrachlorosilane silicon nitride films 应用四氯硅烷氮化硅薄膜实现无硼渗透的高性能双栅dram

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934980

M. Tanaka, S. Saida, F. Inoue, M. Kojima, T. Nakanishi, K. Suguro, Y. Tsunashima

{"title":"Realization of high performance dual gate DRAMs without boron penetration by application of tetrachlorosilane silicon nitride films","authors":"M. Tanaka, S. Saida, F. Inoue, M. Kojima, T. Nakanishi, K. Suguro, Y. Tsunashima","doi":"10.1109/VLSIT.2001.934980","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934980","url":null,"abstract":"It is well known that conventional SiN films accelerate boron penetration due to hydrogen desorption during a high temperature annealing process after SiN deposition (Pfiester et al, 1990). The boron penetration causes depletion of the gate electrodes and threshold voltage deviations, and degrades the PMOSFETs. In the case of next generation DRAMs, thick SiN films are necessary as a hard mask for a self-aligned contact (SAC) process to increase the density. Simultaneously, dual gate CMOS systems should be applied to realize high performance. Therefore, SiN films without boron penetration must be developed for realization of dual gate CMOS systems with a SAC process. Conventional silicon nitride (SiN) films accelerate boron penetration, which causes the degradation of PMOSFETs. It was found that boron penetration becomes worse in proportion to SiH content incorporated in SiN LPCVD films. Applications of SiH-less SiN films, formed from tetrachlorosilane (TCS) and ammonia, have successfully realized the high performance of PMOSFETs in dual gate system DRAMs.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128893747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3