High performance sub-60 nm SOI MOSFETs with 1.2 nm thick nitride/oxide gate dielectric

Abstract

High performance sub-60 nm SOI CMOS transistors have been developed. An aggressively scaled, 1.2 nm thick, gate dielectric sandwich containing silicon nitride and dioxide layers allowed full control of boron penetration with manageable levels of gate leakage. Excellent values of I/sub dsat/ of 850 /spl mu/A//spl mu/m and 500 /spl mu/A//spl mu/m for NMOS and PMOS were respectively obtained at V/sub dd/=1.2 V and I/sub off/=100 nA//spl mu/m. The CV/I metric was 1.0 and 1.9 ps for NMOS and PMOS respectively.