2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)最新文献

Consistent model for short-channel nMOSFET post-hard-breakdown characteristics 短沟道nMOSFET硬击穿后特性的一致性模型

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934979

B. Kaczer, R. Degraeve, A. De Keersgieter, K. Van de Mieroop, T. Bearda, G. Groeseneken

引用次数: 17

A strategy for long data retention time of 512 Mb DRAM with 0.12 /spl mu/m design rule 基于0.12 /spl mu/m设计规则的512 Mb DRAM长数据保留策略

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934930

H. Uh, J.K. Lee, Y. Ahn, S. Lee, S. Hong, J. Lee, G. Koh, G. Jeong, T. Chung, Kinam Kim

引用次数: 2

Asymmetric source/drain extension transistor structure for high performance sub-50 nm gate length CMOS devices 非对称源漏扩展晶体管结构，用于高性能低于50 nm栅极长度的CMOS器件

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934925

T. Ghani, K. Mistry, P. Packan, M. Armstrong, S. Thompson, S. Tyagi, M. Bohr

引用次数: 23

Impact of CMOS process scaling and SOI on the soft error rates of logic processes CMOS制程缩放和SOI对逻辑制程软错误率的影响

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934953

S. Hareland, J. Maiz, M. Alavi, K. Mistry, Steve Walsta, C. Dai

引用次数: 141

Gate voltage dependent model for TDDB lifetime prediction under direct tunneling regime 直接隧穿条件下TDDB寿命预测的门电压依赖模型

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934968

M. Takayanagi, S. Takagi, Y. Toyoshima

引用次数: 2

Scalability and biasing strategy for CMOS with active well bias 有源井偏置CMOS的可扩展性和偏置策略

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934972

Shih-Fen Huang, C. Wann, Yu-Shyang Huang, Chih-Yung Lin, T. Schafbauer, Shui-Ming Cheng, Yao-Ching Cheng, D. Vietzke, M. Eller, Chuan Lin, Q. Ye, N. Rovedo, S. Biesemans, P. Nguyen, R. Dennard, Bomy Chen

{"title":"Scalability and biasing strategy for CMOS with active well bias","authors":"Shih-Fen Huang, C. Wann, Yu-Shyang Huang, Chih-Yung Lin, T. Schafbauer, Shui-Ming Cheng, Yao-Ching Cheng, D. Vietzke, M. Eller, Chuan Lin, Q. Ye, N. Rovedo, S. Biesemans, P. Nguyen, R. Dennard, Bomy Chen","doi":"10.1109/VLSIT.2001.934972","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934972","url":null,"abstract":"We analyze the scalability of the two well bias strategies: reverse bias to reduce standby power, and forward bias to improve the speed or to reduce active power. We then present the device design space that includes well bias as an integral part of the design variables following the SIA Roadmap specifications. We show that proper well biases are needed for bulk CMOS just to continue to meet the SIA Roadmap requirements for performance and standby current. The scalabilities for forward bias and reverse bias are different. The advantage of reverse bias is diminishing with scaling due to low initial V/sub t/ values, short-channel effects, and band-to-band tunneling. The advantage of the forward body bias is preserved better with scaling due to high initial V/sub t/ values as well as smaller depletion width, and increases with V/sub t/ nonscaling. The forward bias approach is not effective in speed improvement for ultra-high performance applications with high V/sub dd/ overdrive and low V/sub t/ to start with, but is effective in active power reduction at a fixed speed target.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133461509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

A multi-gate dielectric technology using hydrogen pre-treatment for 100 nm generation system-on-a-chip 采用氢预处理的多栅极介电技术用于100nm生成的片上系统

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934956

A. Ono, K. Fukasaku, T. Hirai, M. Makabe, S. Koyama, N. Ikezawa, K. Ando, T. Suzuki, K. Imai, N. Nakamura

引用次数: 1

Controlling base-SiO/sub 2/ density of low-leakage 1.6 nm gate-SiON for high-performance and highly reliable n/pFETs 控制低漏1.6 nm栅极-硅基sio /sub 2/密度，用于高性能和高可靠的n/ pfet

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934957

M. Togo, K. Watanabe, M. Terai, S. Kimura, A. Morioka, T. Yamamoto, T. Tatsumi, T. Mogami

引用次数: 7

Impact of vias on the thermal effect of deep sub-micron Cu/low-k interconnects 过孔对深亚微米Cu/低k互连热效应的影响

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934989

TingYen Chiang, K. Saraswat

引用次数: 10

Fabrication of a novel vertical pMOSFET with enhanced drive current and reduced short-channel effects and floating body effects 具有增强驱动电流、减少短通道效应和浮体效应的新型垂直pMOSFET的制造

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934943

Q. Ouyang, Xiangdong Chen, A. Tasch, L. Register, S. Banerjee, J. Chu, J. Ott

引用次数: 2