A. Ono, K. Fukasaku, T. Hirai, M. Makabe, S. Koyama, N. Ikezawa, K. Ando, T. Suzuki, K. Imai, N. Nakamura
{"title":"采用氢预处理的多栅极介电技术用于100nm生成的片上系统","authors":"A. Ono, K. Fukasaku, T. Hirai, M. Makabe, S. Koyama, N. Ikezawa, K. Ando, T. Suzuki, K. Imai, N. Nakamura","doi":"10.1109/VLSIT.2001.934956","DOIUrl":null,"url":null,"abstract":"A multi-gate dielectric technology using hydrogen pre-treatment has been developed for 100-nm generation CMOS technologies. This process can remove the chemical oxide layer and smoothes the Si surface before gate-oxidation to improve interface carrier mobility as well as reliability of 1.3 nm ultra-thin gate dielectric film. In multi-oxide processing, the hydrogen pretreatment does not affect the performance or yield in the thick gate region (1.6-3.4 nm). Using this technology, we have achieved I/sub D//sup sat/ of 780 /spl mu/A//spl mu/m (I/sub OFF/=25 nA//spl mu/m) and 305 /spl mu/A//spl mu/m (I/sub OFF/=30 nA//spl mu/m) for 70-nm nMOS and pMOS, respectively, with 1.3 nm gate dielectric at 1.0 V operation. In addition to the performance improvement, the reliability in terms of TDDB and NBTI (negative bias temperature instability) were also improved.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A multi-gate dielectric technology using hydrogen pre-treatment for 100 nm generation system-on-a-chip\",\"authors\":\"A. Ono, K. Fukasaku, T. Hirai, M. Makabe, S. Koyama, N. Ikezawa, K. Ando, T. Suzuki, K. Imai, N. Nakamura\",\"doi\":\"10.1109/VLSIT.2001.934956\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A multi-gate dielectric technology using hydrogen pre-treatment has been developed for 100-nm generation CMOS technologies. This process can remove the chemical oxide layer and smoothes the Si surface before gate-oxidation to improve interface carrier mobility as well as reliability of 1.3 nm ultra-thin gate dielectric film. In multi-oxide processing, the hydrogen pretreatment does not affect the performance or yield in the thick gate region (1.6-3.4 nm). Using this technology, we have achieved I/sub D//sup sat/ of 780 /spl mu/A//spl mu/m (I/sub OFF/=25 nA//spl mu/m) and 305 /spl mu/A//spl mu/m (I/sub OFF/=30 nA//spl mu/m) for 70-nm nMOS and pMOS, respectively, with 1.3 nm gate dielectric at 1.0 V operation. In addition to the performance improvement, the reliability in terms of TDDB and NBTI (negative bias temperature instability) were also improved.\",\"PeriodicalId\":232773,\"journal\":{\"name\":\"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)\",\"volume\":\"92 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2001.934956\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2001.934956","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A multi-gate dielectric technology using hydrogen pre-treatment for 100 nm generation system-on-a-chip
A multi-gate dielectric technology using hydrogen pre-treatment has been developed for 100-nm generation CMOS technologies. This process can remove the chemical oxide layer and smoothes the Si surface before gate-oxidation to improve interface carrier mobility as well as reliability of 1.3 nm ultra-thin gate dielectric film. In multi-oxide processing, the hydrogen pretreatment does not affect the performance or yield in the thick gate region (1.6-3.4 nm). Using this technology, we have achieved I/sub D//sup sat/ of 780 /spl mu/A//spl mu/m (I/sub OFF/=25 nA//spl mu/m) and 305 /spl mu/A//spl mu/m (I/sub OFF/=30 nA//spl mu/m) for 70-nm nMOS and pMOS, respectively, with 1.3 nm gate dielectric at 1.0 V operation. In addition to the performance improvement, the reliability in terms of TDDB and NBTI (negative bias temperature instability) were also improved.