{"title":"过孔对深亚微米Cu/低k互连热效应的影响","authors":"TingYen Chiang, K. Saraswat","doi":"10.1109/VLSIT.2001.934989","DOIUrl":null,"url":null,"abstract":"This paper investigates in detail the impact of vias on the thermal characteristics of high performance Cu/low-k interconnects. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the dielectric material used. An efficient 3D electro-thermal simulation methodology is presented to evaluate the temperature profile along wires and the thermal coupling between them. The possibility that the thermal effect may degrade the expected speed improvement from the use of low-k dielectrics is discussed. Finally, the more realistic RC performances of various low-k schemes, under the impact of thermal effects, are examined.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"31 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Impact of vias on the thermal effect of deep sub-micron Cu/low-k interconnects\",\"authors\":\"TingYen Chiang, K. Saraswat\",\"doi\":\"10.1109/VLSIT.2001.934989\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper investigates in detail the impact of vias on the thermal characteristics of high performance Cu/low-k interconnects. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the dielectric material used. An efficient 3D electro-thermal simulation methodology is presented to evaluate the temperature profile along wires and the thermal coupling between them. The possibility that the thermal effect may degrade the expected speed improvement from the use of low-k dielectrics is discussed. Finally, the more realistic RC performances of various low-k schemes, under the impact of thermal effects, are examined.\",\"PeriodicalId\":232773,\"journal\":{\"name\":\"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)\",\"volume\":\"31 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2001.934989\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2001.934989","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of vias on the thermal effect of deep sub-micron Cu/low-k interconnects
This paper investigates in detail the impact of vias on the thermal characteristics of high performance Cu/low-k interconnects. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the dielectric material used. An efficient 3D electro-thermal simulation methodology is presented to evaluate the temperature profile along wires and the thermal coupling between them. The possibility that the thermal effect may degrade the expected speed improvement from the use of low-k dielectrics is discussed. Finally, the more realistic RC performances of various low-k schemes, under the impact of thermal effects, are examined.