高性能60nm以下SOI mosfet, 1.2 nm厚氮化物/氧化物栅极电介质

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934952

W. Maszara, S. Krishnan, Q. Xiang, M. Lin

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引用次数: 3

摘要

高性能60nm以下SOI CMOS晶体管已经开发出来。1.2 nm厚的栅极介电夹层包含氮化硅和二氧化硅层，可以在可控的栅极泄漏水平下完全控制硼的渗透。在V/sub dd/=1.2 V和I/sub off/=100 nA//spl mu/m时，NMOS和PMOS的I/sub dsat/分别为850 /spl mu/A//spl mu/m和500 /spl mu/A//spl mu/m。NMOS和PMOS的CV/I分别为1.0和1.9 ps。

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High performance sub-60 nm SOI MOSFETs with 1.2 nm thick nitride/oxide gate dielectric

High performance sub-60 nm SOI CMOS transistors have been developed. An aggressively scaled, 1.2 nm thick, gate dielectric sandwich containing silicon nitride and dioxide layers allowed full control of boron penetration with manageable levels of gate leakage. Excellent values of I/sub dsat/ of 850 /spl mu/A//spl mu/m and 500 /spl mu/A//spl mu/m for NMOS and PMOS were respectively obtained at V/sub dd/=1.2 V and I/sub off/=100 nA//spl mu/m. The CV/I metric was 1.0 and 1.9 ps for NMOS and PMOS respectively.

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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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