一种基于0.15 /spl mu/m逻辑的嵌入式DRAM技术，采用MIM(金属-绝缘体-金属)电容器，具有0.425 /spl mu/m/sup 2/堆叠单元

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934931

M. Takeuchi, K. Inoue, M. Sakao, T. Sakoh, T. Kitamura, S. Arai, T. Iizuka, T. Yamamoto, H. Shirai, Y. Aoki, M. Hamada, R. Kubota, S. Kishi

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引用次数: 2

摘要

我们开发了嵌入式DRAM技术，0.15 /spl mu/m逻辑晶体管性能与纯逻辑工艺完全兼容。关键技术是新开发的W-TiN-Ta/sub - 2/O/sub - 5/-TiN结构的MIM电容元件。对于这种MIM电容器元件的形成过程，低至500/spl度/C的温度就足够了。在125/spl度/C下，获得了8/spl倍/10/sup -15/ A//spl μ /m/sup 2/， T/sub eq/(等效氧化物厚度)为17 /spl Aring/的优异泄漏电流特性。该技术已实际实现在4 Mbit测试芯片中，单元尺寸为0.425 /spl mu/m/sup 2/。在无冗余的情况下，获得了50%以上的成品率，证实了工艺集成中不存在基本问题。

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A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor

We have developed embedded DRAM technology, in which 0.15 /spl mu/m logic transistor performance is fully compatible with that of pure logic processes. The key technology is the newly developed MIM capacitor element with W-TiN-Ta/sub 2/O/sub 5/-TiN structure. Temperatures as low as 500/spl deg/C are sufficient for the formation process for this MIM capacitor element. Excellent leakage current characteristics of 8/spl times/10/sup -15/ A//spl mu/m/sup 2/ at 125/spl deg/C with T/sub eq/ (equivalent oxide thickness) of 17 /spl Aring/ have been obtained. This technology has been actually implemented into a 4 Mbit test chip with cell size of 0.425 /spl mu/m/sup 2/. Over 50% yield without redundancy was obtained, confirming that there are no basic issues in process integration.

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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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