2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)最新文献_第4页

Non-uniform chip-temperature dependent signal integrity 非均匀芯片温度相关的信号完整性

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934991

A. Ajami, K. Banerjee, Massoud Pedram

引用次数: 9

Realization of high performance dual gate DRAMs without boron penetration by application of tetrachlorosilane silicon nitride films 应用四氯硅烷氮化硅薄膜实现无硼渗透的高性能双栅dram

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934980

M. Tanaka, S. Saida, F. Inoue, M. Kojima, T. Nakanishi, K. Suguro, Y. Tsunashima

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引用次数: 3

Effects of high-/spl kappa/ dielectrics on the workfunctions of metal and silicon gates 高/声压级kappa/电介质对金属和硅栅极工作性能的影响

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934941

Y. Yeo, P. Ranade, Q. Lu, R. Lin, T. King, C. Hu

引用次数: 23

Oxidation-resistant amorphous TaN barrier for MIM-Ta/sub 2/O/sub 5/ capacitors in giga-bit DRAMs 用于千兆位dram中MIM-Ta/sub 2/O/sub 5/电容器的抗氧化非晶TaN阻挡层

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934936

Y. Nakamura, I. Asano, M. Hiratani, T. Saito, H. Goto

引用次数: 5

Performance improvement of metal gate CMOS technologies 金属栅CMOS技术的性能改进

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934948

S. Matsuda, H. Yamakawa, A. Azuma, Y. Toyoshima

引用次数: 22

A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides 重氮化一氧化氮氧化物CMOS模拟特性的研究

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934964

T. Ohguro, T. Nagano, M. Fujiwara, M. Takayanagi, T. Shimizu, H. Momose, S. Nakamura, Y. Toyoshima

引用次数: 14

A manufacturable 25 nm planar MOSFET technology 一种可制造的25nm平面MOSFET技术

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934933

Y. Ponomarev, J. Loo, C. Dachs, F. Cubaynes, M. Verheijen, M. Kaiser, J. van Berkum, S. Kubicek, J. Bolk, M. Rovers

引用次数: 2

Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding 晶圆键合制备应变硅绝缘子的载流子迁移率增强

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934945

L. Huang, J. Chu, S. Goma, C. D'Emic, S. Koester, D. Canaperi, P. Mooney, S. Cordes, J. Speidell, R. M. Anderson, H.-S.P. Wong

引用次数: 32

A fully planarized 8M bit ferroelectric RAM with 'chain' cell structure 具有“链式”单元结构的全平面化8M位铁电RAM

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934975

T. Ozaki, J. Iba, H. Kanaya, T. Morimoto, O. Hidaka, A. Taniguchi, Y. Kumura, K. Yamakawa, Y. Oowaki, I. Kunishima

引用次数: 2

A high performance 0.12 /spl mu/m CMOS with manufacturable 0.18 /spl mu/m technology 一种高性能0.12 /spl μ m CMOS，可制造0.18 /spl μ m技术

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934970

K. Ichinose, T. Saito, Y. Yanagida, Y. Nonaka, K. Torii, H. Sato, N. Saito, S. Wada, K. Mori, S. Mitani

引用次数: 1