A fully planarized 8M bit ferroelectric RAM with 'chain' cell structure

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934975

T. Ozaki, J. Iba, H. Kanaya, T. Morimoto, O. Hidaka, A. Taniguchi, Y. Kumura, K. Yamakawa, Y. Oowaki, I. Kunishima

引用次数: 2

Abstract

A 8M-bit fully functional ferroelectric RAM (FeRAM) with 0.25 /spl mu/m CMOS process was successfully fabricated by using a highly reliable Pt-SRO-PZT-SRO-Pt stacked capacitor and aluminum reflow based low damage metallization process. The chip area of 76 mm/sup 2/ was achieved by using a 'chain' cell structure.

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具有“链式”单元结构的全平面化8M位铁电RAM

采用高可靠性的Pt-SRO-PZT-SRO-Pt堆叠电容和基于铝流的低损伤金属化工艺，成功制备了0.25 /spl mu/m CMOS工艺的8m位全功能铁电RAM (FeRAM)。通过使用“链式”单元结构，实现了76 mm/sup /的芯片面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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