用于千兆位dram中MIM-Ta/sub 2/O/sub 5/电容器的抗氧化非晶TaN阻挡层

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934936

Y. Nakamura, I. Asano, M. Hiratani, T. Saito, H. Goto

{"title":"用于千兆位dram中MIM-Ta/sub 2/O/sub 5/电容器的抗氧化非晶TaN阻挡层","authors":"Y. Nakamura, I. Asano, M. Hiratani, T. Saito, H. Goto","doi":"10.1109/VLSIT.2001.934936","DOIUrl":null,"url":null,"abstract":"We demonstrate that an amorphous TaN layer with no grain boundaries shows a good oxidation-resistant performance after forming and annealing the Ta/sub 2/O/sub 5/ dielectric of MIM capacitors for DRAM applications at 550/spl deg/C in O/sub 2/ ambient. We fabricated an MIM-Ta/sub 2/O/sub 5/ capacitor with a concave-type Ru storage node on the TaN barrier metal. This showed a contact resistivity of 0.27 k/spl Omega//spl middot//spl mu/m/sup 2/, a capacitance of 20 fF/bit, and a leakage current of 0.9 fA/bit (-1 to 1 V). We further fabricated a crown-type Ru electrode to demonstrate scalability to 0.10 /spl mu/m design rules.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Oxidation-resistant amorphous TaN barrier for MIM-Ta/sub 2/O/sub 5/ capacitors in giga-bit DRAMs\",\"authors\":\"Y. Nakamura, I. Asano, M. Hiratani, T. Saito, H. Goto\",\"doi\":\"10.1109/VLSIT.2001.934936\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate that an amorphous TaN layer with no grain boundaries shows a good oxidation-resistant performance after forming and annealing the Ta/sub 2/O/sub 5/ dielectric of MIM capacitors for DRAM applications at 550/spl deg/C in O/sub 2/ ambient. We fabricated an MIM-Ta/sub 2/O/sub 5/ capacitor with a concave-type Ru storage node on the TaN barrier metal. This showed a contact resistivity of 0.27 k/spl Omega//spl middot//spl mu/m/sup 2/, a capacitance of 20 fF/bit, and a leakage current of 0.9 fA/bit (-1 to 1 V). We further fabricated a crown-type Ru electrode to demonstrate scalability to 0.10 /spl mu/m design rules.\",\"PeriodicalId\":232773,\"journal\":{\"name\":\"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2001.934936\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2001.934936","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

我们证明了在550/spl度/C、O/sub / 2/环境下形成和退火用于DRAM的MIM电容器的Ta/sub / 2/O/sub / 5/介质后，无晶界的非晶态TaN层具有良好的抗氧化性能。我们在TaN阻挡金属上制作了一种具有凹型Ru存储节点的MIM-Ta/sub 2/O/sub 5/电容器。结果表明，接触电阻率为0.27 k/spl ω //spl middot//spl mu/m/sup 2/，电容为20 fF/bit，漏电流为0.9 fA/bit(-1至1 V)。我们进一步制作了一个冠状Ru电极，以证明可扩展性到0.10 /spl mu/m的设计规则。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Oxidation-resistant amorphous TaN barrier for MIM-Ta/sub 2/O/sub 5/ capacitors in giga-bit DRAMs

We demonstrate that an amorphous TaN layer with no grain boundaries shows a good oxidation-resistant performance after forming and annealing the Ta/sub 2/O/sub 5/ dielectric of MIM capacitors for DRAM applications at 550/spl deg/C in O/sub 2/ ambient. We fabricated an MIM-Ta/sub 2/O/sub 5/ capacitor with a concave-type Ru storage node on the TaN barrier metal. This showed a contact resistivity of 0.27 k/spl Omega//spl middot//spl mu/m/sup 2/, a capacitance of 20 fF/bit, and a leakage current of 0.9 fA/bit (-1 to 1 V). We further fabricated a crown-type Ru electrode to demonstrate scalability to 0.10 /spl mu/m design rules.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

自引率

0.00%

发文量