Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934945

L. Huang, J. Chu, S. Goma, C. D'Emic, S. Koester, D. Canaperi, P. Mooney, S. Cordes, J. Speidell, R. M. Anderson, H.-S.P. Wong

引用次数: 32

Abstract

N- and p-MOSFETs have been fabricated in strained Si on SiGe on insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 46% for electrons and 60-80% for holes (for 20%-25% Ge content) has been demonstrated in SSOI MOSFETs. This could lead to next generation device performance enhancement.

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晶圆键合制备应变硅绝缘子的载流子迁移率增强

在高锗含量(15-25%)的绝缘子(SSOI)上，在应变Si上制备了N-和p- mosfet。晶圆键合和h诱导层转移技术使高锗含量绝缘体上硅基板(SGOI)的制造成为可能。在SSOI mosfet中，电子的迁移率提高了46%，空穴的迁移率提高了60-80% (Ge含量为20%-25%)。这可能会导致下一代设备的性能增强。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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