2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)最新文献_第5页

High performance 40 nm vertical MOSFET within a conventional CMOS process flow 高性能40纳米垂直MOSFET在传统的CMOS工艺流程

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934944

E. Josse, T. Skotnicki, M. Jurczak, M. Paoli, B. Tormen, D. Dufartre, P. Ribot, A. Villaret, E. Søndergård

引用次数: 3

High performance sub-50 nm CMOS with advanced gate stack 高性能低于50纳米CMOS与先进的栅极堆栈

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934928

Q. Xiang, B. Yu, H. Wang, M. Lin

引用次数: 8

A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs 高性能100纳米一代SOC技术(CMOS IV)，用于高密度嵌入式存储器和混合信号lsi

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934922

K. Miyashita, T. Nakayama, A. Oishi, R. Hasumi, M. Owada, S. Aota, Y. Okayama, M. Matsumoto, H. Igarashi, T. Yoshida, K. Kasai, T. Yoshitomi, Y. Fukaura, H. Kawasaki, K. Ishimaru, K. Adachi, M. Fujiwara, K. Ohuchi, M. Takayanagi, H. Oyamatsu, F. Matsuoka, T. Noguchi, M. Kakumu

引用次数: 14

Experimental and simulation study on sub-50 nm CMOS design sub- 50nm CMOS设计的实验与仿真研究

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934934

S. Pidin, H. Shido, T. Yamamoto, N. Horiguchi, H. Kurata, T. Sugii

引用次数: 10

Design technology for systems on a chip 芯片上系统的设计技术

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1007/978-0-387-35597-9_8

R. Camposano, D. MacMillen

引用次数: 5

DRAM scaling-down to 0.1 /spl mu/m generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug 采用位线无间隔存储节点SAC和带TiN触点插头的RIR电容，将DRAM缩小到0.1 /spl mu/m

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934982

B. Jin, Young-pil Kim, B. Nam, H. Kim, Young-wook Park, J. Moon

{"title":"DRAM scaling-down to 0.1 /spl mu/m generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug","authors":"B. Jin, Young-pil Kim, B. Nam, H. Kim, Young-wook Park, J. Moon","doi":"10.1109/VLSIT.2001.934982","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934982","url":null,"abstract":"As DRAM downscaling approaches the 0.1 /spl mu/m generation, problems related to transistor short channel effects, storage capacitance, gap filling of high aspect ratio patterns, and leakage currents through each module must be solved. Among these, processing around the storage node self-aligned contact (SAC) is the most critical problem for integration of capacitor-on-bitline (COB) DRAM devices because it is one of the deepest contacts with high aspect ratio; and it reaches the cell transistor junction. However, few reports have addressed this issue, while others have been reported elsewhere (Song et al., 2000; Jeong et al., 2000; Won et al., 2000; Kim et al., 2000). In this paper, a novel process of bitline spacerless storage node SAC and Ru-Ta/sub 2/O/sub 5/-Ru (RIR) capacitor with TiN contact plug is studied for the integration of 0.1 /spl mu/m design-rule based DRAMs. It was found that the spacerless SAC process made downscaling to the 0.1 /spl mu/m design-rule possible and also that it has better electrical properties than the conventional SAC.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134358307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Barrier-metal-free (BMF), Cu dual-damascene interconnects with Cu-epi-contacts buried in anti-diffusive, low-k organic film 无金属障碍(BMF)，铜双大马士革互连与铜外延触点埋在抗扩散，低k有机薄膜

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934923

M. Tada, H. Ohtake, Y. Harada, M. Hiroi, S. Saito, T. Onodera, N. Furutake, J. Kawahara, M. Tagami, K. Kinoshita, T. Fukai, T. Mogami, Y. Hayashi

{"title":"Barrier-metal-free (BMF), Cu dual-damascene interconnects with Cu-epi-contacts buried in anti-diffusive, low-k organic film","authors":"M. Tada, H. Ohtake, Y. Harada, M. Hiroi, S. Saito, T. Onodera, N. Furutake, J. Kawahara, M. Tagami, K. Kinoshita, T. Fukai, T. Mogami, Y. Hayashi","doi":"10.1109/VLSIT.2001.934923","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934923","url":null,"abstract":"Barrier-metal-free (BMF) Cu dual-damascene interconnects (DDI) are fabricated in the plasma-polymerized, divinyl siloxane bis-benzocyclobutene (p-BCB: k=2.6) polymer film, which is characterised by anti-diffusive characteristics for the Cu. The BMF-structure has inter-line leakage current as low as that of a conventional barrier-inserted structure and is estimated to retain the high insulating properties for over 10 years under 1 MV/cm stress. The BMF-structure also derives Cu-epi-contacts, reducing the via-resistance to 50% of that of the conventional Cu/barrier/Cu contacts. The effective dielectric constant was k/sub eff/=3.1, including very thin SiN etch-stop-layers, accomplishing 20% faster CMOS device operation compared to that of the conventional Cu-DDI in the SiO/sub 2/ with Ta-TaN barriers. The BMF Cu-DDIs buried directly in the p-BCB film is one of the ultimate structures for high performance, 0.1 /spl mu/m-CMOS devices and beyond.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129972463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A 0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM working cell with LPRD (low parasitic resistance device) and poly metal gate technology for gigabit DRAM 一个0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM工作单元，采用LPRD(低寄生电阻器件)和多金属栅极技术用于千兆DRAM

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934929

Hyunpil Noh, Woncheol Cho, G. Jeong, M. Huh, Jaemin Ahn, Y.S. Kim, Suock Jeong, Seongjoon Lee, Dongseok Kim, Hazoong Kim, J. Suh, Jinwon Park, Sang-Don Lee, H. Yoon

引用次数: 0

Ultra-thin ZrO/sub 2/ (or silicate) with high thermal stability for CMOS gate applications 超薄ZrO/sub 2/(或硅酸盐)具有高热稳定性，适用于CMOS栅极应用

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934986

Z. Luo, T. Ma, E. Cartier, M. Copel, T. Tamagawa, B. Halpern

{"title":"Ultra-thin ZrO/sub 2/ (or silicate) with high thermal stability for CMOS gate applications","authors":"Z. Luo, T. Ma, E. Cartier, M. Copel, T. Tamagawa, B. Halpern","doi":"10.1109/VLSIT.2001.934986","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934986","url":null,"abstract":"With the dramatic scaling of the CMOS devices, ZrO/sub 2/ and its silicates (Qi et al., 1999; Ma et al., 1999) are considered to be among the most promising candidates to replace conventional SiO/sub 2/ as gate dielectrics. In this study, we report on the electrical and physical properties of ultra-thin Zr silicate/ZrO/sub 2/ films deposited by the jet-vapor-deposition (JVD) process (Guo et al., 1998). Both MOS capacitors and NMOSFETs were successfully fabricated. It is shown that films with equivalent oxide thickness (EOT) of 1 nm possess high thermal stability, low leakage, high reliability and other good electrical properties. Our analysis also shows that the composition of JVD films varies with thickness. Thinner films are found to be Zr silicate-like, whereas thicker films are likely graded with a transition to stoichiometric ZrO/sub 2/. The presence of a thermally stable Zr silicate layer may prevent the formation of interfacial SiO/sub 2/, despite the fact that as-deposited films are found to be oxygen rich. In contrast to most other ZrO/sub 2/ films reported in the literature, the EOTs of our films decrease after post deposition annealing. In addition, these films were found to survive annealing temperatures as high as 1000/spl deg/C, suggesting that JVD ZrO/sub 2//silicate can be used in a conventional CMOS process without the need for a replacement gate process.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125861455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

New considerations for highly reliable PMOSFETs in 100 nm generation and beyond 100纳米及以后高可靠性pmosfet的新考虑

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934977

E. Morifuji, T. Kumamori, M. Muta, K. Suzuki, I. De, A. Shibkov, S. Saxena, T. Enda, N. Aoki, W. Asano, H. Otani, M. Nishigori, K. Miyamoto, F. Matsuoka, T. Noguchi, M. Kakumu

引用次数: 6