Experimental and simulation study on sub-50 nm CMOS design

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934934

S. Pidin, H. Shido, T. Yamamoto, N. Horiguchi, H. Kurata, T. Sugii

引用次数: 10

Abstract

CMOS devices with gate lengths down to sub-50 nm were fabricated using poly-Si gates with notches and conventional gate structures. It was shown that an optimal halo, as compared to conventional gates, is achieved when a tilted implant is performed using gates with notches. Due to optimal halo placement, up to 7% improvement in drain current for p-MOS and 15% improvement for n-MOS and simultaneously 20 nm improvement in threshold voltage roll-off were observed for notched gate devices for the same extension implant.

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sub- 50nm CMOS设计的实验与仿真研究

采用带缺口的多晶硅栅极和传统栅极结构制备栅极长度小于50 nm的CMOS器件。结果表明，与传统门相比，当使用带缺口的门进行倾斜种植时，可以获得最佳的光晕。由于最佳的光晕放置，对于相同扩展植入物的缺口栅器件，p-MOS的漏极电流提高了7%，n-MOS的漏极电流提高了15%，同时阈值电压滚降提高了20 nm。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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