High performance 40 nm vertical MOSFET within a conventional CMOS process flow

Abstract

We present here 40 nm vertical MOSFETs fabricated using the most standard CMOS process flow. At the expense of four additional (but still conventional) steps, both planar and vertical devices can be co-integrated within the same flow. Our process is fully described and the vertical transistors are characterized. Very good device performances are obtained at 1 V supply voltage with relaxed gate oxide thickness. Therefore, our vertical MOSFET may constitute an interesting alternative for high performance planar devices in case aggressive scaling of oxide thickness fails.