Z. Luo, T. Ma, E. Cartier, M. Copel, T. Tamagawa, B. Halpern
{"title":"Ultra-thin ZrO/sub 2/ (or silicate) with high thermal stability for CMOS gate applications","authors":"Z. Luo, T. Ma, E. Cartier, M. Copel, T. Tamagawa, B. Halpern","doi":"10.1109/VLSIT.2001.934986","DOIUrl":null,"url":null,"abstract":"With the dramatic scaling of the CMOS devices, ZrO/sub 2/ and its silicates (Qi et al., 1999; Ma et al., 1999) are considered to be among the most promising candidates to replace conventional SiO/sub 2/ as gate dielectrics. In this study, we report on the electrical and physical properties of ultra-thin Zr silicate/ZrO/sub 2/ films deposited by the jet-vapor-deposition (JVD) process (Guo et al., 1998). Both MOS capacitors and NMOSFETs were successfully fabricated. It is shown that films with equivalent oxide thickness (EOT) of 1 nm possess high thermal stability, low leakage, high reliability and other good electrical properties. Our analysis also shows that the composition of JVD films varies with thickness. Thinner films are found to be Zr silicate-like, whereas thicker films are likely graded with a transition to stoichiometric ZrO/sub 2/. The presence of a thermally stable Zr silicate layer may prevent the formation of interfacial SiO/sub 2/, despite the fact that as-deposited films are found to be oxygen rich. In contrast to most other ZrO/sub 2/ films reported in the literature, the EOTs of our films decrease after post deposition annealing. In addition, these films were found to survive annealing temperatures as high as 1000/spl deg/C, suggesting that JVD ZrO/sub 2//silicate can be used in a conventional CMOS process without the need for a replacement gate process.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2001.934986","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
With the dramatic scaling of the CMOS devices, ZrO/sub 2/ and its silicates (Qi et al., 1999; Ma et al., 1999) are considered to be among the most promising candidates to replace conventional SiO/sub 2/ as gate dielectrics. In this study, we report on the electrical and physical properties of ultra-thin Zr silicate/ZrO/sub 2/ films deposited by the jet-vapor-deposition (JVD) process (Guo et al., 1998). Both MOS capacitors and NMOSFETs were successfully fabricated. It is shown that films with equivalent oxide thickness (EOT) of 1 nm possess high thermal stability, low leakage, high reliability and other good electrical properties. Our analysis also shows that the composition of JVD films varies with thickness. Thinner films are found to be Zr silicate-like, whereas thicker films are likely graded with a transition to stoichiometric ZrO/sub 2/. The presence of a thermally stable Zr silicate layer may prevent the formation of interfacial SiO/sub 2/, despite the fact that as-deposited films are found to be oxygen rich. In contrast to most other ZrO/sub 2/ films reported in the literature, the EOTs of our films decrease after post deposition annealing. In addition, these films were found to survive annealing temperatures as high as 1000/spl deg/C, suggesting that JVD ZrO/sub 2//silicate can be used in a conventional CMOS process without the need for a replacement gate process.