2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)最新文献_第6页

50 nm SOI CMOS transistors with ultra shallow junction using laser annealing and pre-amorphization implantation 采用激光退火和预非晶化注入的50 nm超浅结SOI CMOS晶体管

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934951

Cheolmin Park, Seong-Dong Kim, Y. Wang, S. Talwar, J. Woo

引用次数: 10

Cylindrical Ru-SrTiO/sub 3/-Ru capacitor technology for 0.11 /spl mu/m generation DRAMs 用于0.11 /spl mu/m一代dram的圆柱形Ru-SrTiO/sub - 3/-Ru电容技术

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934938

C. M. Chu, M. Kiyotoshi, S. Niwa, J. Nakahira, K. Eguchi, S. Yamazaki, K. Tsunoda, M. Fukuda, T. Suzuki, M. Nakabayashi, H. Tomita, C. Shiah, D. Matsunaga, K. Hieda

引用次数: 1

Transistor-limited constant voltage stress of gate dielectrics 栅极电介质的晶体管限制恒压应力

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934965

B. Linder, D. Frank, J. Stathis, S. Cohen

引用次数: 25

Manufacturing in the 21st century-new concept for 300 mm fab 制造在21世纪的新概念为300毫米晶圆厂

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934918

A. Koike

引用次数: 9

Performance and reliability of ultra thin CVD HfO/sub 2/ gate dielectrics with dual poly-Si gate electrodes 具有双多晶硅栅极的超薄CVD HfO/sub / gate介质的性能和可靠性

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934985

S.J. Lee, H. Luan, C. Lee, T. Jeon, W. Bai, Y. Senzaki, D. Roberts, D. Kwong

引用次数: 50

Low resistivity bcc-Ta/TaN/sub x/ metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450/spl deg/C 具有平面栅极结构的低电阻率bcc-Ta/TaN/sub - x/金属栅极mnsfet，具有低于450/spl度/C的完全低温处理功能

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934950

H. Shimada, I. Ohshima, S. Nakao, M. Nakagawa, K. Kanemoto, M. Hirayama, S. Sugawa, T. Ohmi

引用次数: 6

Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM 门体隧穿电流对PD/SOI CMOS SRAM的影响

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934954

R. Joshi, C. Chuang, S. Fung, F. Assaderaghi, M. Sherony, I. Yang, G. Shahidi

{"title":"Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM","authors":"R. Joshi, C. Chuang, S. Fung, F. Assaderaghi, M. Sherony, I. Yang, G. Shahidi","doi":"10.1109/VLSIT.2001.934954","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934954","url":null,"abstract":"The gate tunneling current for gate oxide thickness around 2.0 nm or below has been known to increase device leakage and power dissipation, and deteriorate device performance and circuit stability in bulk CMOS. Recently, direct tunneling current models for bulk CMOS circuit simulations have been developed (Choi et al., 1999; Lee and Hu, 2000). The gate-to-substrate tunneling current resulting from the electron tunneling from the valence band (EVB) is significantly less than the tunneling current from the channel into the gate, and its effect can usually be neglected in bulk CMOS devices and circuits. For floating-body partially-depleted (PD) SOI devices, however, the gate-to-body tunneling current charges/discharges the floating-body, thus changing the body voltage and V/sub T/ and affecting circuit operation (Fung et al., 2000). In this paper, we present a detailed study of the effect of gate tunneling current on a high performance 34 Kb L1 directory SRAM in a 1.5 V, 0.18 /spl mu/m PD/SOI technology with L/sub eff/=0.08 /spl mu/m and t/sub ox/=2.3 /spl mu/m. This SRAM was originally designed in a 1.5 V, 0.18 /spl mu/m bulk CMOS technology and has achieved 2.0 GHz cycle time and 430 ps access time (Joshi et al., 2000). It utilizes pseudo-static circuits for robust timing and to facilitate migration to PD/SOI technology.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128006386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications 一个0.13 /spl mu/m CMOS平台，具有Cu/低k互连，用于片上系统应用

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934969

T. Schiml, S. Biesemans, G. Brase, L. Burrell, A. Cowley, K. Chen, A. von Ehrenwall, B. von Ehrenwall, P. Felsner, J. Gill, F. Grellner, F. Guarín, L. Han, M. Hoinkis, E. Hsiung, E. Kaltalioglu, P. Kim, G. Knoblinger, S. Kulkarni, A. Leslie, T. Mono, T. Schafbauer, U. Schroeder, K. Schruefer, T. Spooner, D. Warner, C. Wang, R. Wong, E. Demm, P. Leung

引用次数: 55

A new quantitative hydrogen-based model for ultra-thin oxide breakdown 一种新的超薄氧化物击穿定量氢基模型

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934967

J. Suñé, E. Wu

引用次数: 35

Metal gate work function adjustment for future CMOS technology 金属栅极工作功能调整为未来CMOS技术

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934939

Q. Lu, R. Lin, P. Ranade, T. King, C. Hu

引用次数: 42