Performance and reliability of ultra thin CVD HfO/sub 2/ gate dielectrics with dual poly-Si gate electrodes

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934985

S.J. Lee, H. Luan, C. Lee, T. Jeon, W. Bai, Y. Senzaki, D. Roberts, D. Kwong

引用次数: 50

Abstract

MOSFETs with high quality ultra thin (EOT/spl sim/10.3 /spl Aring/) HfO/sub 2/ gate stacks and self-aligned dual poly-Si gate are fabricated and characterized. Both n- and p-MOSFETs show good electron and hole mobility, respectively, and excellent sub-threshold swings. In addition, the HfO/sub 2/ gate stack exhibits excellent thermal stability with poly-Si gates up to 1050/spl deg/C/30 s gate activation annealing and shows excellent TDDB reliability characteristics with negligible charge trapping and SILC under high-field stressing.

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具有双多晶硅栅极的超薄CVD HfO/sub / gate介质的性能和可靠性

制备了具有高质量超薄(EOT/spl sim/10.3 /spl Aring/) HfO/sub - 2/栅极和自对准双多晶硅栅极的mosfet，并对其进行了表征。n-和p- mosfet分别表现出良好的电子和空穴迁移率，以及优异的亚阈值振荡。此外，HfO/sub - 2/栅极堆栈具有优异的热稳定性，其栅极活化退火温度高达1050/spl℃/30 s，并且具有优异的TDDB可靠性，在高场应力下可以忽略电荷捕获和SILC。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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