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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)最新文献

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Impact of low-standby-power device design on hot carrier reliability 低备用功率器件设计对热载波可靠性的影响
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934978
E. Murakami, K. Umeda, T. Yamanaka, S. Kimura, H. Aono, K. Makabe, K. Okuyama, Y. Ohji, Y. Yoshida, M. Minami, K. Kuroda, S. Ikeda, K. Kubota
{"title":"Impact of low-standby-power device design on hot carrier reliability","authors":"E. Murakami, K. Umeda, T. Yamanaka, S. Kimura, H. Aono, K. Makabe, K. Okuyama, Y. Ohji, Y. Yoshida, M. Minami, K. Kuroda, S. Ikeda, K. Kubota","doi":"10.1109/VLSIT.2001.934978","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934978","url":null,"abstract":"The hot-carrier (HC) reliability of low-standby-power 0.1 /spl mu/m n-MOSFETs is investigated, and design guidelines for channel and halo profiles are described. The heavy channel-doping needed to obtain high V/sub th/ enhances HC-injection efficiency, and heavy halo-doping dramatically reduces the lifetime when using substrate-bias (V/sub bb/). Shallow-channel and tilted-halo doping is optimal to keep the HC-generation site away from the SiO/sub 2/-Si interface and to minimize the vertical electric field that is responsible for secondary impact ionization.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133908097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Scaling scenario of multi-level interconnects for future CMOS LSI 未来CMOS LSI的多级互连扩展方案
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934990
H. Yoshimura, Y. Asahi, F. Matsuoka
{"title":"Scaling scenario of multi-level interconnects for future CMOS LSI","authors":"H. Yoshimura, Y. Asahi, F. Matsuoka","doi":"10.1109/VLSIT.2001.934990","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934990","url":null,"abstract":"Scaling guidelines for multi-level interconnects for future CMOS LSI are presented. They are based upon intensive circuit simulation combined with a 2D field solver while considering the wire length distribution of logic circuits. Interconnect structures such as metal aspect ratio and ILD thickness are optimized to minimize wiring delay without causing crosstalk problems. In addition, the scaling factors of future BEOL parameters are presented.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133636255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Shallow n/sup +//p/sup +/ junction formation using plasma immersion ion implantation for CMOS technology 利用等离子体浸没离子注入形成浅n/sup +//p/sup +/结
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934927
Kil-Ho Lee, J. Sim, Yujun Li, W. Kang, R. Malik, R. Rengarajan, S. Chaloux, J. Bernstein, P. Kellerman
{"title":"Shallow n/sup +//p/sup +/ junction formation using plasma immersion ion implantation for CMOS technology","authors":"Kil-Ho Lee, J. Sim, Yujun Li, W. Kang, R. Malik, R. Rengarajan, S. Chaloux, J. Bernstein, P. Kellerman","doi":"10.1109/VLSIT.2001.934927","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934927","url":null,"abstract":"We present CMOS transistors with n/sup +//p/sup +/ source/drain extensions doped by AsH/sub 3/ and BF/sub 3/ plasma immersion ion implantation (PIII) for the first time. We successfully demonstrate n/sup +//p/sup +/ shallow junctions with R/sub s/<1 k/spl Omega//sq for CMOS devices. No degradation in gate oxide integrity is observed for either AsH/sub 3/ or BF/sub 3/ PIII. Compared to conventional ion implantation, PIII provides much better short-channel effects and approximately 50% I/sub off/ reduction for both nMOS and pMOS devices. In particular, the flat threshold voltage roll-off and good performance in buried-channel pMOS devices is the best-reported PIII data to date.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131003275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Optimization of annealing conditions for dual damascene Cu microstructures and via chain yields 双damascene Cu微结构退火条件优化及通孔链产率
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934988
Qing-Tang Jiang, A. Frank, R. Havemann, V. Parihar, M. Nowell
{"title":"Optimization of annealing conditions for dual damascene Cu microstructures and via chain yields","authors":"Qing-Tang Jiang, A. Frank, R. Havemann, V. Parihar, M. Nowell","doi":"10.1109/VLSIT.2001.934988","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934988","url":null,"abstract":"The effect of different post electroplating anneals on dual damascene Cu microstructures and via chain yields using both rapid thermal processing and furnace anneal were investigated. It was found that the grain size, [111] texture, Cu line resistance, and dual damascene Cu via chain yields varied strongly with the annealing conditions. The minimum feature size of trench width or height imposes physical limits on the average grain size. Via chain yield failure analysis was also carried out using SEM cross sections.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132650624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Novel damage-free direct metal gate process using atomic layer deposition 采用原子层沉积的新型无损伤直接金属栅极工艺
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934949
Dae-gyu Park, K. Lim, Heung-Jae Cho, Taeho Cha, Joong-Jung Kim, Jung-Kyu Ko, I. Yeo, J. Park
{"title":"Novel damage-free direct metal gate process using atomic layer deposition","authors":"Dae-gyu Park, K. Lim, Heung-Jae Cho, Taeho Cha, Joong-Jung Kim, Jung-Kyu Ko, I. Yeo, J. Park","doi":"10.1109/VLSIT.2001.934949","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934949","url":null,"abstract":"We report the impact of atomic layer deposition (ALD)-TiN on the novel characteristics of the W/TiN/SiO/sub 2//p-Si MOS system. A damage-free direct metal gate was attained using ALD-TiN as manifested by the negligible hysteresis and low interface trap density (D/sub it/) of /spl sim/5/spl times/10/sup 10/ eV/sup -1/cm/sup -2/ near the Si midgap. Gate leakage current level gated with ALD-TiN is remarkably lower than that with physical vapor deposition (PVD)-TiN or poly-Si gate at a similar capacitance equivalent thickness (CET). In addition, ALD-TiN demonstrated highly robust gate oxide reliability with negligible CET variation against high thermal budget, paving the way for the direct metal gate process.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116514146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Ge-redistributed poly-Si/SiGe stack gate (GRPSG) for high-performance CMOSFETs 用于高性能cmosfet的ge重分布多晶硅/硅堆叠栅极(GRPSG)
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934947
H. Rhee, G. Bae, T. Choe, S.S. Kim, S. Song, N. Lee, K. Fujihara, H. Kang, J. Moon
{"title":"Ge-redistributed poly-Si/SiGe stack gate (GRPSG) for high-performance CMOSFETs","authors":"H. Rhee, G. Bae, T. Choe, S.S. Kim, S. Song, N. Lee, K. Fujihara, H. Kang, J. Moon","doi":"10.1109/VLSIT.2001.934947","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934947","url":null,"abstract":"A Ge-redistributed poly-Si/SiGe stack gate (GRPSG) has been proposed to improve the current performance of PMOS without the degradation of NMOS for sub-0.1 /spl mu/m CMOSFETs with ultrathin gate oxide. Ge diffusion into the poly-Si layer was promoted more by ion implantation of N-type dopants such as P and As rather than P-type dopants. NMOS and PMOS had different Ge concentrations at the interface between gate electrode and gate oxide by an additional anneal to redistribute the Ge profile. The current performance of NMOS with GRPSG with low Ge content (<5%) was not degraded, while that of PMOS with GRPSG with high Ge content (>20%) was improved due to suppression of the poly-depletion effect and boron penetration. In addition, the gate reoxidation was modified to reduce G/sub m/ degradation by reduced gate bird's beak. High-performance 70 nm-CMOSFETs were successfully fabricated using the simple GRPSG process.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124599369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel analysis method of threshold voltage shift due to detrap in a multi-level flash memory 一种新的多电平快闪存储器中陷阱阈值电压漂移分析方法
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934976
R. Yamada, T. Sekiguchi, Y. Okuyama, J. Yugami, H. Kume
{"title":"A novel analysis method of threshold voltage shift due to detrap in a multi-level flash memory","authors":"R. Yamada, T. Sekiguchi, Y. Okuyama, J. Yugami, H. Kume","doi":"10.1109/VLSIT.2001.934976","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934976","url":null,"abstract":"With the aim of improving flash-memory retention characteristics, we investigated threshold voltage shift (/spl Delta/V/sub th/) due to charge detrapping from the tunnel oxide. Accordingly, we propose a new parameter that can reveal the main origin of detrapping (hole/electron) and the detrap centroid. We found that the main origin of detrapping changes from holes to electrons depending on the degree of tunnel-oxide degradation. Since the hole detrapping increases V/sub th/ of a programmed memory cell, this V/sub th/ increase must be considered, especially when designing a multi-level flash memory.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132613077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Ultra-thin body PMOSFETs with selectively deposited Ge source/drain 具有选择性沉积Ge源/漏极的超薄体pmosfet
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934926
Yang-Kyu Choi, Daewon Ha, T. King, C. Hu
{"title":"Ultra-thin body PMOSFETs with selectively deposited Ge source/drain","authors":"Yang-Kyu Choi, Daewon Ha, T. King, C. Hu","doi":"10.1109/VLSIT.2001.934926","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934926","url":null,"abstract":"Ultra-thin body (UTB) MOSFETs with body thickness down to 4 nm and LPCVD selectively deposited Ge raised source and drain (S/D) are demonstrated for the first time. Devices with gate length down to 30 nm show excellent short-channel behavior. Mobility enhancement and threshold-voltage shift due to the quantum confinement of inversion charge by the ultra-thin body are investigated.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129890092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 0.13-/spl mu/m SOI CMOS technology for low-power digital and RF applications 0.13-/spl mu/m SOI CMOS技术，适用于低功耗数字和射频应用
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934959
N. Zamdmer, A. Ray, J. Plouchart, L. Wagner, N. Fong, K. Jenkins, W. Jin, P. Smeys, I. Yang, G. Shahidi, F. Assaderghi
{"title":"A 0.13-/spl mu/m SOI CMOS technology for low-power digital and RF applications","authors":"N. Zamdmer, A. Ray, J. Plouchart, L. Wagner, N. Fong, K. Jenkins, W. Jin, P. Smeys, I. Yang, G. Shahidi, F. Assaderghi","doi":"10.1109/VLSIT.2001.934959","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934959","url":null,"abstract":"Battery-operated electronic devices that can communicate wirelessly are becoming more and more pervasive. This trend is enabled by technologies that allow low-power digital and RF processing. We present here a 0.13 /spl mu/m, partially-depleted SOI CMOS technology with optimized power-saving and RF properties. Power-saving features include low-V/sub t/, thin-gate-oxide FETs for minimum power dissipation and high performance at low voltage (25 ps inverter delay at 0.7 V V/sub dd/); high-V/sub t/, thick-gate-oxide FETs for low-standby-power SRAM and logic-block power switches; and eight levels of Cu interconnects with low-k ILD (Smeys et al., 2000). RF features include high peak NFET performance (141 GHz f/sub T/ and 98 GHz f/sub max/ at V/sub ds/=1.2 V) and the following group of high-Q passives: inductor (peak simulated differential Q of 50 at 4 GHz, L=0.65 nH), MOS varactor, MIMCAP, and resistors.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123351316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Statistical analysis of soft breakdown in ultrathin gate oxides 超薄栅极氧化物软击穿的统计分析
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI: 10.1109/VLSIT.2001.934966
W. Mizubayashi, Y. Yoshida, S. Miyazaki, M. Hirose
{"title":"Statistical analysis of soft breakdown in ultrathin gate oxides","authors":"W. Mizubayashi, Y. Yoshida, S. Miyazaki, M. Hirose","doi":"10.1109/VLSIT.2001.934966","DOIUrl":"https://doi.org/10.1109/VLSIT.2001.934966","url":null,"abstract":"It is found that the Weibull slope /spl beta/ of the time-to-soft breakdown (t/sub SBD/) distributions coincides with that of time-to-hard breakdown (t/sub BD/) distributions over the oxide thickness range 1.9-4.8 nm, and /spl beta/ linearly decreases with decrease of oxide thickness. Such decrease in /spl beta/ of both t/sub SBD/ and t/sub BD/ distributions is well correlated to measured Si-O-Si bond angle reduction induced by compressive stress in the SiO/sub 2/ network. These results suggest that soft breakdown (SBD) as well as hard breakdown (HBD) are triggered by a common physical mechanism such as defect generation from strained Si-O-Si bonds.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124694500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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