Scaling scenario of multi-level interconnects for future CMOS LSI

Abstract

Scaling guidelines for multi-level interconnects for future CMOS LSI are presented. They are based upon intensive circuit simulation combined with a 2D field solver while considering the wire length distribution of logic circuits. Interconnect structures such as metal aspect ratio and ILD thickness are optimized to minimize wiring delay without causing crosstalk problems. In addition, the scaling factors of future BEOL parameters are presented.