未来CMOS LSI的多级互连扩展方案

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934990

H. Yoshimura, Y. Asahi, F. Matsuoka

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引用次数: 3

摘要

提出了未来CMOS LSI多层互连的尺度准则。它们是基于密集的电路仿真，并结合二维场求解器，同时考虑了逻辑电路的导线长度分布。互连结构，如金属宽高比和ILD厚度进行了优化，以尽量减少布线延迟，而不会引起串扰问题。此外，还提出了未来BEOL参数的标度因子。

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Scaling scenario of multi-level interconnects for future CMOS LSI

Scaling guidelines for multi-level interconnects for future CMOS LSI are presented. They are based upon intensive circuit simulation combined with a 2D field solver while considering the wire length distribution of logic circuits. Interconnect structures such as metal aspect ratio and ILD thickness are optimized to minimize wiring delay without causing crosstalk problems. In addition, the scaling factors of future BEOL parameters are presented.

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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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