采用原子层沉积的新型无损伤直接金属栅极工艺

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934949

Dae-gyu Park, K. Lim, Heung-Jae Cho, Taeho Cha, Joong-Jung Kim, Jung-Kyu Ko, I. Yeo, J. Park

{"title":"采用原子层沉积的新型无损伤直接金属栅极工艺","authors":"Dae-gyu Park, K. Lim, Heung-Jae Cho, Taeho Cha, Joong-Jung Kim, Jung-Kyu Ko, I. Yeo, J. Park","doi":"10.1109/VLSIT.2001.934949","DOIUrl":null,"url":null,"abstract":"We report the impact of atomic layer deposition (ALD)-TiN on the novel characteristics of the W/TiN/SiO/sub 2//p-Si MOS system. A damage-free direct metal gate was attained using ALD-TiN as manifested by the negligible hysteresis and low interface trap density (D/sub it/) of /spl sim/5/spl times/10/sup 10/ eV/sup -1/cm/sup -2/ near the Si midgap. Gate leakage current level gated with ALD-TiN is remarkably lower than that with physical vapor deposition (PVD)-TiN or poly-Si gate at a similar capacitance equivalent thickness (CET). In addition, ALD-TiN demonstrated highly robust gate oxide reliability with negligible CET variation against high thermal budget, paving the way for the direct metal gate process.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"Novel damage-free direct metal gate process using atomic layer deposition\",\"authors\":\"Dae-gyu Park, K. Lim, Heung-Jae Cho, Taeho Cha, Joong-Jung Kim, Jung-Kyu Ko, I. Yeo, J. Park\",\"doi\":\"10.1109/VLSIT.2001.934949\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report the impact of atomic layer deposition (ALD)-TiN on the novel characteristics of the W/TiN/SiO/sub 2//p-Si MOS system. A damage-free direct metal gate was attained using ALD-TiN as manifested by the negligible hysteresis and low interface trap density (D/sub it/) of /spl sim/5/spl times/10/sup 10/ eV/sup -1/cm/sup -2/ near the Si midgap. Gate leakage current level gated with ALD-TiN is remarkably lower than that with physical vapor deposition (PVD)-TiN or poly-Si gate at a similar capacitance equivalent thickness (CET). In addition, ALD-TiN demonstrated highly robust gate oxide reliability with negligible CET variation against high thermal budget, paving the way for the direct metal gate process.\",\"PeriodicalId\":232773,\"journal\":{\"name\":\"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2001.934949\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2001.934949","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 17

摘要

我们报道了原子层沉积(ALD)-TiN对W/TiN/SiO/sub 2/ p-Si MOS体系新特性的影响。利用ALD-TiN制备了一种无损伤的直接金属栅极，其滞回可以忽略，界面阱密度(D/sub /)为/spl sim/5/spl倍/10/sup 10/ eV/sup -1/cm/sup -2/。在相似电容等效厚度(CET)下，ALD-TiN栅极漏电流明显低于物理气相沉积(PVD)-TiN或多晶硅栅极。此外，ALD-TiN表现出高度稳健的栅极氧化物可靠性，在高热预算下，CET变化可以忽略不计，为直接金属栅极工艺铺平了道路。

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Novel damage-free direct metal gate process using atomic layer deposition

We report the impact of atomic layer deposition (ALD)-TiN on the novel characteristics of the W/TiN/SiO/sub 2//p-Si MOS system. A damage-free direct metal gate was attained using ALD-TiN as manifested by the negligible hysteresis and low interface trap density (D/sub it/) of /spl sim/5/spl times/10/sup 10/ eV/sup -1/cm/sup -2/ near the Si midgap. Gate leakage current level gated with ALD-TiN is remarkably lower than that with physical vapor deposition (PVD)-TiN or poly-Si gate at a similar capacitance equivalent thickness (CET). In addition, ALD-TiN demonstrated highly robust gate oxide reliability with negligible CET variation against high thermal budget, paving the way for the direct metal gate process.

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来源期刊

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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