Low resistivity bcc-Ta/TaN/sub x/ metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450/spl deg/C

Abstract

We have developed a low-resistivity metal gate metal-nitride-semiconductor (MNS) FET technology with conventional plane gate structure using fully low-temperature processing. The gate stack consists of directly grown silicon nitride (Si/sub 3/N/sub 4/) dielectric using high-density plasma and bcc-phase tantalum (/spl sim/15 /spl mu//spl Omega/cm)/tantalum nitride (bcc-Ta/TaN/sub x/) stacked metal gate below 1.0 /spl Omega//sq. In order to avoid deterioration of the metal gate system, we adopted low-temperature S/D annealing by the solid phase epitaxy (SPE) method. In this paper, we demonstrate the excellent characteristics of fully-depleted silicon-on-dielectric (FDSOI) metal gate MNSFETs with conventional plane gate structure using fully low-temperature processing below 450/spl deg/C.