具有平面栅极结构的低电阻率bcc-Ta/TaN/sub - x/金属栅极mnsfet，具有低于450/spl度/C的完全低温处理功能

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934950

H. Shimada, I. Ohshima, S. Nakao, M. Nakagawa, K. Kanemoto, M. Hirayama, S. Sugawa, T. Ohmi

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引用次数: 6

摘要

我们开发了一种低电阻率金属栅极金属氮化半导体(MNS)场效应管技术，采用传统的平面栅极结构，采用全低温加工。栅极堆叠由高密度等离子体直接生长的氮化硅(Si/sub 3/N/sub 4/)电介质和bcc相钽(/spl sim/15 /spl mu//spl Omega/cm)/氮化钽(bcc-Ta/TaN/sub x/)堆叠的低于1.0 /spl Omega//sq的金属栅极组成。为了避免金属栅系统的劣化，我们采用固相外延(SPE)方法进行低温S/D退火。在本文中，我们展示了具有传统平面栅极结构的全耗尽介电硅(FDSOI)金属栅极mnsfet的优异特性，并使用低于450/spl℃的全低温处理。

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Low resistivity bcc-Ta/TaN/sub x/ metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450/spl deg/C

We have developed a low-resistivity metal gate metal-nitride-semiconductor (MNS) FET technology with conventional plane gate structure using fully low-temperature processing. The gate stack consists of directly grown silicon nitride (Si/sub 3/N/sub 4/) dielectric using high-density plasma and bcc-phase tantalum (/spl sim/15 /spl mu//spl Omega/cm)/tantalum nitride (bcc-Ta/TaN/sub x/) stacked metal gate below 1.0 /spl Omega//sq. In order to avoid deterioration of the metal gate system, we adopted low-temperature S/D annealing by the solid phase epitaxy (SPE) method. In this paper, we demonstrate the excellent characteristics of fully-depleted silicon-on-dielectric (FDSOI) metal gate MNSFETs with conventional plane gate structure using fully low-temperature processing below 450/spl deg/C.

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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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