L. Huang, J. Chu, S. Goma, C. D'Emic, S. Koester, D. Canaperi, P. Mooney, S. Cordes, J. Speidell, R. M. Anderson, H.-S.P. Wong
{"title":"晶圆键合制备应变硅绝缘子的载流子迁移率增强","authors":"L. Huang, J. Chu, S. Goma, C. D'Emic, S. Koester, D. Canaperi, P. Mooney, S. Cordes, J. Speidell, R. M. Anderson, H.-S.P. Wong","doi":"10.1109/VLSIT.2001.934945","DOIUrl":null,"url":null,"abstract":"N- and p-MOSFETs have been fabricated in strained Si on SiGe on insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 46% for electrons and 60-80% for holes (for 20%-25% Ge content) has been demonstrated in SSOI MOSFETs. This could lead to next generation device performance enhancement.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":"{\"title\":\"Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding\",\"authors\":\"L. Huang, J. Chu, S. Goma, C. D'Emic, S. Koester, D. Canaperi, P. Mooney, S. Cordes, J. Speidell, R. M. Anderson, H.-S.P. Wong\",\"doi\":\"10.1109/VLSIT.2001.934945\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"N- and p-MOSFETs have been fabricated in strained Si on SiGe on insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 46% for electrons and 60-80% for holes (for 20%-25% Ge content) has been demonstrated in SSOI MOSFETs. This could lead to next generation device performance enhancement.\",\"PeriodicalId\":232773,\"journal\":{\"name\":\"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"32\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2001.934945\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2001.934945","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding
N- and p-MOSFETs have been fabricated in strained Si on SiGe on insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 46% for electrons and 60-80% for holes (for 20%-25% Ge content) has been demonstrated in SSOI MOSFETs. This could lead to next generation device performance enhancement.