A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor

Abstract

We have developed embedded DRAM technology, in which 0.15 /spl mu/m logic transistor performance is fully compatible with that of pure logic processes. The key technology is the newly developed MIM capacitor element with W-TiN-Ta/sub 2/O/sub 5/-TiN structure. Temperatures as low as 500/spl deg/C are sufficient for the formation process for this MIM capacitor element. Excellent leakage current characteristics of 8/spl times/10/sup -15/ A//spl mu/m/sup 2/ at 125/spl deg/C with T/sub eq/ (equivalent oxide thickness) of 17 /spl Aring/ have been obtained. This technology has been actually implemented into a 4 Mbit test chip with cell size of 0.425 /spl mu/m/sup 2/. Over 50% yield without redundancy was obtained, confirming that there are no basic issues in process integration.