High-density and high-performance 6T-SRAM for system-on-chip in 130 nm CMOS technology

Abstract

We have developed the smallest high density 6T-SRAM cell (1.87 /spl mu/m/sup 2/) reported to date in 130 nm CMOS logic process for system-on-chip (SOC) applications. We have also developed an ultra-high speed 6T-SRAM cell (2.49 /spl mu/m/sup 2/) with cell current of 116 /spl mu/A for SOC applications requiring even higher performance. These were achieved using our systematic SRAM technology development methodology and optimized OPC capability. These cells do not require additional process steps and use 248 nm lithography, making them very attractive for low-cost SOC manufacturing.