Deep sub-micron CMOS device design for low power analog applications

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934960

H. Deshpande, B. Cheng, J. Woo

引用次数: 9

Abstract

Signal swing, power and device performance requirements for analog applications result in trade-offs for scaled MOSFET design. This paper presents a comprehensive study on optimization of deep sub-micron NMOS device for low power analog applications. It is shown that novel channel engineering is essential along with thin gate oxides and shallow junctions for improving the device analog performance.

查看原文本刊更多论文

低功耗模拟应用的深亚微米CMOS器件设计

模拟应用的信号摆幅，功率和器件性能要求导致缩放MOSFET设计的权衡。本文对用于低功耗模拟应用的深亚微米NMOS器件的优化进行了全面的研究。研究表明，为了提高器件的模拟性能，新型通道工程以及薄栅氧化物和浅结是必不可少的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

自引率

0.00%

发文量