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Proceedings of Bipolar/Bicmos Circuits and Technology Meeting最新文献

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Predictive modelling of lateral scaling in bipolar transistors 双极晶体管横向缩放的预测模型
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493870
D. Walkey, M. Schroter, S. Voinigescu
{"title":"Predictive modelling of lateral scaling in bipolar transistors","authors":"D. Walkey, M. Schroter, S. Voinigescu","doi":"10.1109/BIPOL.1995.493870","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493870","url":null,"abstract":"A new approach for modelling the dependence of bipolar transistor characteristics on emitter width and length is presented. The new model, verified by device simulation and measurement, predicts device behavior accurately over a wide range of emitter aspect ratios.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116068271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The p-MOS controlled lateral thyristor: A MOS controllable thyristor suitable for integration p-MOS可控横向晶闸管:一种适用于集成的MOS可控晶闸管
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493898
W. Chen, G. Amaratunga
{"title":"The p-MOS controlled lateral thyristor: A MOS controllable thyristor suitable for integration","authors":"W. Chen, G. Amaratunga","doi":"10.1109/BIPOL.1995.493898","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493898","url":null,"abstract":"A novel CMOS compatible lateral thyristor is proposed in this paper. Its thyristor conduction is fully controlled by a p-MOS gate. Loss of MOS control due to parasitic latch-up has been eliminated and triggering of the main thyristor at lower forward current achieved. The device operation has been verified by 2D numerical simulations and experimental fabrication.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122974600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evidence for nonequilibrium base transport in Si and SiGe bipolar transistors at cryogenic temperatures 低温下Si和SiGe双极晶体管非平衡基底输运的证据
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493860
D. M. Richey, A. Joseph, J. Cressler, R. Jaeger
{"title":"Evidence for nonequilibrium base transport in Si and SiGe bipolar transistors at cryogenic temperatures","authors":"D. M. Richey, A. Joseph, J. Cressler, R. Jaeger","doi":"10.1109/BIPOL.1995.493860","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493860","url":null,"abstract":"Observed discrepancies between measured collector current and transconductance with that predicted by standard drift-diffusion theory at cryogenic temperatures are explained by accounting for nonequilibrium carrier transport across the neutral base region in advanced Si and SiGe bipolar devices.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130580444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 200 mm SiGe-HBT BiCMOS technology for mixed signal applications 用于混合信号应用的200mm SiGe-HBT BiCMOS技术
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493873
D. Nguyen-ngoc, D. Harame, J. Malinowski, S. Jeng, K. Schonenberg, M. Gilbert, G. Berg, S. Wu, M. Soyuer, K. Tallman, K. Stein, R. Groves, S. Subbanna, D. Colavito, D. Sunderland, B. Meyerson
{"title":"A 200 mm SiGe-HBT BiCMOS technology for mixed signal applications","authors":"D. Nguyen-ngoc, D. Harame, J. Malinowski, S. Jeng, K. Schonenberg, M. Gilbert, G. Berg, S. Wu, M. Soyuer, K. Tallman, K. Stein, R. Groves, S. Subbanna, D. Colavito, D. Sunderland, B. Meyerson","doi":"10.1109/BIPOL.1995.493873","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493873","url":null,"abstract":"A BiCMOS technology including 0.25 /spl mu/m electrical channel length (L/sub EFF/) nFET and pFET CMOS devices and 60 GHz f/sub max/ SiGe-HBT transistors has been achieved on 200 mm wafers. Both CMOS circuits and SiGe-HBT analog circuits were fabricated on the same chip to demonstrate the high integration capabilities of the technology. The CMOS circuits include CMOS ring oscillators and a 64 k SRAM with a 34 /spl mu/m/sup 2/ cell size. The SiGe-HBT circuits include ECL ring oscillators and a Voltage Controlled Oscillator (VCO). This is the highest level of integration yet achieved for any SiGe-base bipolar technology.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131801167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A 3 V supply voltage, DC-18 GHz SiGe HBT wideband amplifier 一个3 V电源电压，DC-18 GHz sigehbt宽带放大器
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493895
H. Schumacher, A. Gruhle, U. Erben, H. Kibbel, U. Konig
{"title":"A 3 V supply voltage, DC-18 GHz SiGe HBT wideband amplifier","authors":"H. Schumacher, A. Gruhle, U. Erben, H. Kibbel, U. Konig","doi":"10.1109/BIPOL.1995.493895","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493895","url":null,"abstract":"We report a wideband, low power consumption monolithic amplifier using SiGe heterojunction bipolar transistors which, at 50 mW power consumption, provides 9.5 dB of gain from DC through 18 GHz, with 5.3 dB noise figure. 1.6 V operation is possible with slight bandwidth reduction to 15 GHz, and less than 20 mW power consumption.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124128035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
VBIC95: An improved vertical, IC bipolar transistor model VBIC95:一个改进的垂直，集成电路双极晶体管模型
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493891
C. McAndrew, J. Seitchik, D. Bowers, M. Dunn, M. Foisy, I. Getreu, M. McSwain, S. Moinian, J. Parker, P. van Wijnen, L. Wagner
{"title":"VBIC95: An improved vertical, IC bipolar transistor model","authors":"C. McAndrew, J. Seitchik, D. Bowers, M. Dunn, M. Foisy, I. Getreu, M. McSwain, S. Moinian, J. Parker, P. van Wijnen, L. Wagner","doi":"10.1109/BIPOL.1995.493891","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493891","url":null,"abstract":"This paper presents a vertical BJT model developed by IC and CAD industry representatives as a replacement for the SPICE Gummel-Poon model. VBIC95 includes improved modeling of the Early effect (output conductance), substrate current, quasi-saturation, and behavior over temperature.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126731049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
AIDE (Angle-Implanted Drain and Emitter): A BiCMOS technology module for mixed-signal applications AIDE(角度植入漏极和发射极):用于混合信号应用的BiCMOS技术模块
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493885
Hung-sheng Chen, Ji Zhao, C. Teng, L. Leu
{"title":"AIDE (Angle-Implanted Drain and Emitter): A BiCMOS technology module for mixed-signal applications","authors":"Hung-sheng Chen, Ji Zhao, C. Teng, L. Leu","doi":"10.1109/BIPOL.1995.493885","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493885","url":null,"abstract":"Increased mixed-signal device performance and reliability in a BiCMOS technology is achieved by using Angle-Implanted Drain and Emitter (AIDE) technology. An order of magnitude increase in lifetime is obtained in MOS/BJT transistors, while a >40% increase in transistor gain is achieved. This technology module is applicable to existing BiCMOS process with minimum increase in process complexity.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133345912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Improved collector transit time with ballistic pipi-structure in the npn-AlGaAs/GaAs HBT 在npn-AlGaAs/GaAs HBT中采用弹道管状结构改善集电极传输时间
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493861
D.M. Kim, S.H. Song
{"title":"Improved collector transit time with ballistic pipi-structure in the npn-AlGaAs/GaAs HBT","authors":"D.M. Kim, S.H. Song","doi":"10.1109/BIPOL.1995.493861","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493861","url":null,"abstract":"In this paper, we propose an improved npn-HBT with pipi-doping collector structure maximally utilizing ballistic transport property with modified electric field distribution in the collector-base space charge region. With pipi-HBT, we obtained significant reduction of /spl tau//sub scr/ compared with those of previously reported conventional and ballistic collector structure HBTs.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115879152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
1.5 /spl mu/m analog BiCMOS/DMOS process for medium voltage and current power ICs applications up to 50 V 1.5 /spl mu/m模拟BiCMOS/DMOS工艺，适用于高达50 V的中压和电流功率ic应用
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493884
M. El-Diwany, J. McGregor, E. Demirliogiu, R. Huang
{"title":"1.5 /spl mu/m analog BiCMOS/DMOS process for medium voltage and current power ICs applications up to 50 V","authors":"M. El-Diwany, J. McGregor, E. Demirliogiu, R. Huang","doi":"10.1109/BIPOL.1995.493884","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493884","url":null,"abstract":"ABCD150 is a 1.5 /spl mu/m analog BiCMOS/DMOS process. It addresses power ICs for medium voltage and current applications up to 50 V. Four types of power MOS transistors are available; low voltage MOS; high voltage MOS; vertical DMOS; and HV lateral DMOS. Each is optimized for minimum specific on resistance R/sub ds/(on) (in /spl Omega/.mm/sup 2/) at their respective operating voltages.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"540 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123459135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Signal isolation in BiCMOS mixed mode integrated circuits BiCMOS混合模式集成电路中的信号隔离
Proceedings of Bipolar/Bicmos Circuits and Technology Meeting Pub Date : 1995-10-02 DOI: 10.1109/BIPOL.1995.493892
K. Joardar
{"title":"Signal isolation in BiCMOS mixed mode integrated circuits","authors":"K. Joardar","doi":"10.1109/BIPOL.1995.493892","DOIUrl":"https://doi.org/10.1109/BIPOL.1995.493892","url":null,"abstract":"Comparing several cross-talk reduction schemes using two-dimensional device simulation and measurements on silicon has shown that while SOI based processes provide high isolation from cross-talk, fully junction isolated wells can provide equal or better cross-talk immunity at a lesser expense. Simple guard ring substrate contacts appear to be the technique best suited for preventing cross-talk at high operating frequencies. A lumped parameter equivalent circuit has also been developed to simulate fully junction isolated wells in SPICE.","PeriodicalId":230944,"journal":{"name":"Proceedings of Bipolar/Bicmos Circuits and Technology Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130277192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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